From 22e725cabd170a8e9e667f56862e53f80827f5f2 Mon Sep 17 00:00:00 2001
From: eigmax <stephen@ieigen.com>
Date: Thu, 26 Oct 2023 08:46:05 +0800
Subject: [PATCH] feat: impl register and cpu

---
 src/cpu/bootstrap_kernel.rs | 2 ++
 src/cpu/kernel/assembler.rs | 4 ++++
 src/cpu/kernel/load_elf.rs  | 2 +-
 src/generation/mod.rs       | 1 +
 src/witness/memory.rs       | 5 +++--
 src/witness/transition.rs   | 2 ++
 6 files changed, 13 insertions(+), 3 deletions(-)

diff --git a/src/cpu/bootstrap_kernel.rs b/src/cpu/bootstrap_kernel.rs
index f2fd1a0c..53607f7e 100644
--- a/src/cpu/bootstrap_kernel.rs
+++ b/src/cpu/bootstrap_kernel.rs
@@ -26,6 +26,8 @@ pub(crate) fn generate_bootstrap_kernel<F: Field>(state: &mut GenerationState<F>
 
         // Write this chunk to memory, while simultaneously packing its bytes into a u32 word.
         for (channel, (addr, &byte)) in chunk.enumerate() {
+            // FIXME: should all be in the MainMemory. Both instruction and memory data are located in
+            // memory section for MIPS
             let address = MemoryAddress::new(0, Segment::Code, addr);
             let write =
                 mem_write_gp_log_and_fill(channel, address, state, &mut cpu_row, byte.into());
diff --git a/src/cpu/kernel/assembler.rs b/src/cpu/kernel/assembler.rs
index 271b4268..4b56e43c 100644
--- a/src/cpu/kernel/assembler.rs
+++ b/src/cpu/kernel/assembler.rs
@@ -5,9 +5,13 @@ use std::collections::HashMap;
 
 #[derive(PartialEq, Eq, Debug, Serialize, Deserialize)]
 pub struct Kernel {
+    // MIPS ELF
     pub(crate) code: Vec<u8>,
     pub(crate) code_hash: [u32; 8],
+    // For debugging purposes
     pub(crate) ordered_labels: Vec<String>,
+    // FIXME: precompiled function and global variable, like HALT PC or ecrecover
+    //  should be preprocessed after loading code
     pub(crate) global_labels: HashMap<String, usize>,
 }
 
diff --git a/src/cpu/kernel/load_elf.rs b/src/cpu/kernel/load_elf.rs
index 2e716e87..95daffa3 100644
--- a/src/cpu/kernel/load_elf.rs
+++ b/src/cpu/kernel/load_elf.rs
@@ -103,7 +103,7 @@ mod test {
 
     #[test]
     fn load_and_check_mips_elf() {
-        let mut reader = BufReader::new(File::open("test-vectors/minigeth").unwrap());
+        let mut reader = BufReader::new(File::open("test-vectors/hello").unwrap());
         let mut buffer = Vec::new();
         reader.read_to_end(&mut buffer).unwrap();
         let max_mem = 0x40000000;
diff --git a/src/generation/mod.rs b/src/generation/mod.rs
index 7156ec3f..7176d170 100644
--- a/src/generation/mod.rs
+++ b/src/generation/mod.rs
@@ -88,6 +88,7 @@ pub fn generate_traces<F: RichField + Extendable<D>, const D: usize>(
     Ok((tables, public_values, outputs))
 }
 
+/// Perform MIPS instruction and transit state
 fn simulate_cpu<F: RichField + Extendable<D>, const D: usize>(
     state: &mut GenerationState<F>,
 ) -> anyhow::Result<()> {
diff --git a/src/witness/memory.rs b/src/witness/memory.rs
index c2539702..a67b1020 100644
--- a/src/witness/memory.rs
+++ b/src/witness/memory.rs
@@ -125,6 +125,7 @@ impl MemoryOp {
     }
 }
 
+/// FIXME: all GPRs, HI, LO, EPC and page are also located in memory
 #[derive(Clone, Debug)]
 pub struct MemoryState {
     pub(crate) contexts: Vec<MemoryContextState>,
@@ -132,9 +133,9 @@ pub struct MemoryState {
 
 impl MemoryState {
     pub fn new(kernel_code: &[u8]) -> Self {
-        let code_u256s = kernel_code.iter().map(|&x| x.into()).collect();
+        let code_u32s = kernel_code.iter().map(|&x| x.into()).collect();
         let mut result = Self::default();
-        result.contexts[0].segments[Segment::MainMemory as usize].content = code_u256s;
+        result.contexts[0].segments[Segment::MainMemory as usize].content = code_u32s;
         result
     }
 
diff --git a/src/witness/transition.rs b/src/witness/transition.rs
index 112bd41a..ec9cdbef 100644
--- a/src/witness/transition.rs
+++ b/src/witness/transition.rs
@@ -313,6 +313,8 @@ fn try_perform_instruction<F: Field>(state: &mut GenerationState<F>) -> Result<(
 
     fill_op_flag(op, &mut row);
 
+    // FIXME: decode instruction data, and load IMM and input data into registers
+
     /*
     if state.registers.is_stack_top_read {
         let channel = &mut row.mem_channels[0];