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vivado.log
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vivado.log
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#-----------------------------------------------------------
# Vivado v2017.2 (64-bit)
# SW Build 1909853 on Thu Jun 15 18:39:09 MDT 2017
# IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017
# Start of session at: Sat Apr 28 19:04:22 2018
# Process ID: 2252
# Current directory: f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex
# Command line: vivado.exe -notrace -source f:/Programs/Verilog/FPGA_Group/test_hssi/test_hssi.srcs/sources_1/ip/gtx3g/gtx3g_ex.tcl
# Log file: f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/vivado.log
# Journal file: f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex\vivado.jou
#-----------------------------------------------------------
start_gui
source f:/Programs/Verilog/FPGA_Group/test_hssi/test_hssi.srcs/sources_1/ip/gtx3g/gtx3g_ex.tcl -notrace
INFO: [open_example_project] Creating new example project...
INFO: [IP_Flow 19-234] Refreshing IP repositories
INFO: [IP_Flow 19-1704] No user IP repositories specified
INFO: [IP_Flow 19-2313] Loaded Vivado IP repository 'G:/Xilinx/Vivado/Vivado/2017.2/data/ip'.
create_project: Time (s): cpu = 00:00:18 ; elapsed = 00:00:20 . Memory (MB): peak = 737.941 ; gain = 74.289
INFO: [open_example_project] Importing original IP ...
INFO: [open_example_project] Generating the example project IP ...
INFO: [open_example_project] Adding example synthesis HDL files ...
INFO: [open_example_project] Adding example synthesis miscellaneous files ...
INFO: [open_example_project] Adding example XDC files ...
INFO: [open_example_project] Adding simulation HDL files ...
INFO: [open_example_project] Adding simulation miscellaneous files ...
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'constrs_1'
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'sim_1'
INFO: [filemgmt 20-348] Importing the appropriate files for fileset: 'sources_1'
INFO: [open_example_project] Sourcing example extension scripts ...
INFO: [open_example_project] Rebuilding all the top level IPs ...
INFO: [exportsim-Tcl-35] Exporting simulation files for "XSIM" (Xilinx Vivado Simulator)...
INFO: [exportsim-Tcl-29] Script generated: 'F:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.ip_user_files/sim_scripts/gtx3g/xsim/gtx3g.sh'
INFO: [SIM-utils-43] Exported 'F:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.ip_user_files/sim_scripts/gtx3g/xsim/v7ht.tcl'
INFO: [exportsim-Tcl-35] Exporting simulation files for "MODELSIM" (Mentor Graphics ModelSim Simulator)...
INFO: [exportsim-Tcl-29] Script generated: 'F:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.ip_user_files/sim_scripts/gtx3g/modelsim/gtx3g.sh'
INFO: [SIM-utils-43] Exported 'F:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.ip_user_files/sim_scripts/gtx3g/modelsim/v7ht.tcl'
INFO: [exportsim-Tcl-35] Exporting simulation files for "QUESTA" (Mentor Graphics Questa Advanced Simulator)...
INFO: [exportsim-Tcl-29] Script generated: 'F:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.ip_user_files/sim_scripts/gtx3g/questa/gtx3g.sh'
INFO: [SIM-utils-43] Exported 'F:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.ip_user_files/sim_scripts/gtx3g/questa/v7ht.tcl'
INFO: [exportsim-Tcl-35] Exporting simulation files for "IES" (Cadence Incisive Enterprise Simulator)...
INFO: [exportsim-Tcl-29] Script generated: 'F:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.ip_user_files/sim_scripts/gtx3g/ies/gtx3g.sh'
INFO: [SIM-utils-43] Exported 'F:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.ip_user_files/sim_scripts/gtx3g/ies/v7ht.tcl'
INFO: [exportsim-Tcl-35] Exporting simulation files for "VCS" (Synopsys Verilog Compiler Simulator)...
INFO: [exportsim-Tcl-29] Script generated: 'F:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.ip_user_files/sim_scripts/gtx3g/vcs/gtx3g.sh'
INFO: [SIM-utils-43] Exported 'F:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.ip_user_files/sim_scripts/gtx3g/vcs/v7ht.tcl'
INFO: [exportsim-Tcl-35] Exporting simulation files for "RIVIERA" (Aldec Riviera-PRO Simulator)...
INFO: [exportsim-Tcl-29] Script generated: 'F:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.ip_user_files/sim_scripts/gtx3g/riviera/gtx3g.sh'
INFO: [SIM-utils-43] Exported 'F:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.ip_user_files/sim_scripts/gtx3g/riviera/v7ht.tcl'
INFO: [exportsim-Tcl-35] Exporting simulation files for "ACTIVEHDL" (Aldec Active-HDL Simulator)...
INFO: [exportsim-Tcl-29] Script generated: 'F:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.ip_user_files/sim_scripts/gtx3g/activehdl/gtx3g.sh'
INFO: [SIM-utils-43] Exported 'F:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.ip_user_files/sim_scripts/gtx3g/activehdl/v7ht.tcl'
export_ip_user_files: Time (s): cpu = 00:00:03 ; elapsed = 00:00:05 . Memory (MB): peak = 737.941 ; gain = 0.000
INFO: [open_example_project] Open Example Project completed
update_compile_order -fileset sources_1
add_files -norecurse {F:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/simple_uart.v F:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/gtx3g_test.v F:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/prbs_gen.v F:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/prbs_chk.v}
update_compile_order -fileset sources_1
set_property top gtx3g_test [current_fileset]
update_compile_order -fileset sources_1
set_property SOURCE_SET sources_1 [get_filesets sim_1]
add_files -fileset sim_1 -norecurse F:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sim_1/tb_gtx3g_test.v
update_compile_order -fileset sim_1
set_property top tb_gtx3g_test [get_filesets sim_1]
set_property top_lib xil_defaultlib [get_filesets sim_1]
update_compile_order -fileset sim_1
launch_simulation
INFO: [Vivado 12-4795] Using compiled simulation libraries for IPs
INFO: [SIM-utils-51] Simulation object is 'sim_1'
INFO: [USF-XSim-7] Finding pre-compiled libraries...
INFO: [USF-XSim-11] File 'G:/Xilinx/Vivado/Vivado/2017.2/data/xsim/ip/xsim_ip.ini' copied to run dir:'f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.sim/sim_1/behav'
INFO: [SIM-utils-54] Inspecting design source files for 'tb_gtx3g_test' in fileset 'sim_1'...
INFO: [SIM-utils-43] Exported 'f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.sim/sim_1/behav/gt_rom_init_rx.dat'
INFO: [SIM-utils-43] Exported 'f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.sim/sim_1/behav/gt_rom_init_tx.dat'
INFO: [SIM-utils-43] Exported 'f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.sim/sim_1/behav/gt_rom_init_rx.dat'
INFO: [SIM-utils-43] Exported 'f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.sim/sim_1/behav/gt_rom_init_tx.dat'
INFO: [SIM-utils-43] Exported 'f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.sim/sim_1/behav/gt_rom_init_rx.dat'
INFO: [SIM-utils-43] Exported 'f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.sim/sim_1/behav/gt_rom_init_tx.dat'
INFO: [USF-XSim-97] Finding global include files...
INFO: [USF-XSim-98] Fetching design files from 'sim_1'...
INFO: [USF-XSim-2] XSim::Compile design
INFO: [USF-XSim-61] Executing 'COMPILE and ANALYZE' step in 'f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.sim/sim_1/behav'
"xvlog -m64 --relax -prj tb_gtx3g_test_vlog.prj"
INFO: [VRFC 10-2263] Analyzing Verilog file "f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/ip/gtx3g/gtx3g/example_design/gtx3g_sync_pulse.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module gtx3g_sync_pulse
INFO: [VRFC 10-2263] Analyzing Verilog file "f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/ip/gtx3g/gtx3g/example_design/gtx3g_tx_manual_phase_align.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module gtx3g_TX_MANUAL_PHASE_ALIGN
INFO: [VRFC 10-2263] Analyzing Verilog file "f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/ip/gtx3g/gtx3g/example_design/gtx3g_tx_startup_fsm.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module gtx3g_TX_STARTUP_FSM
INFO: [VRFC 10-2263] Analyzing Verilog file "f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/ip/gtx3g/gtx3g/example_design/gtx3g_rx_startup_fsm.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module gtx3g_RX_STARTUP_FSM
INFO: [VRFC 10-2263] Analyzing Verilog file "f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/ip/gtx3g/gtx3g_init.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module gtx3g_init
INFO: [VRFC 10-2263] Analyzing Verilog file "f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/ip/gtx3g/gtx3g_gt.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module gtx3g_GT
INFO: [VRFC 10-2263] Analyzing Verilog file "f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/ip/gtx3g/gtx3g_multi_gt.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module gtx3g_multi_gt
INFO: [VRFC 10-2263] Analyzing Verilog file "f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/ip/gtx3g/gtx3g/example_design/gtx3g_sync_block.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module gtx3g_sync_block
INFO: [VRFC 10-2263] Analyzing Verilog file "f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/ip/gtx3g/gtx3g.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module gtx3g
INFO: [VRFC 10-2263] Analyzing Verilog file "f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/imports/example_design/support/gtx3g_common.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module gtx3g_common
INFO: [VRFC 10-2263] Analyzing Verilog file "f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/imports/example_design/support/gtx3g_common_reset.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module gtx3g_common_reset
INFO: [VRFC 10-2263] Analyzing Verilog file "f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/imports/example_design/gtx3g_exdes.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module gtx3g_exdes
WARNING: [VRFC 10-1315] redeclaration of ansi port DRPCLK_IN is not allowed [f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/imports/example_design/gtx3g_exdes.v:391]
WARNING: [VRFC 10-1315] redeclaration of ansi port gt0_txusrclk_i is not allowed [f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/imports/example_design/gtx3g_exdes.v:405]
WARNING: [VRFC 10-1315] redeclaration of ansi port q0_clk1_refclk_i is not allowed [f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/imports/example_design/gtx3g_exdes.v:416]
WARNING: [VRFC 10-1315] redeclaration of ansi port gt0_error_count_i is not allowed [f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/imports/example_design/gtx3g_exdes.v:430]
INFO: [VRFC 10-2263] Analyzing Verilog file "f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/imports/example_design/gtx3g_gt_frame_check.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module gtx3g_GT_FRAME_CHECK
WARNING: [VRFC 10-756] identifier data_valid is used before its declaration [f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/imports/example_design/gtx3g_gt_frame_check.v:364]
INFO: [VRFC 10-2263] Analyzing Verilog file "f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/imports/example_design/gtx3g_gt_frame_gen.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module gtx3g_GT_FRAME_GEN
INFO: [VRFC 10-2263] Analyzing Verilog file "f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/imports/example_design/support/gtx3g_gt_usrclk_source.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module gtx3g_GT_USRCLK_SOURCE
INFO: [VRFC 10-2263] Analyzing Verilog file "f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/imports/example_design/support/gtx3g_support.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module gtx3g_support
WARNING: [VRFC 10-1315] redeclaration of ansi port q0_clk1_refclk_i is not allowed [f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/imports/example_design/support/gtx3g_support.v:596]
INFO: [VRFC 10-2263] Analyzing Verilog file "f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/gtx3g_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module gtx3g_test
WARNING: [VRFC 10-1315] redeclaration of ansi port test_succeeded is not allowed [f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/gtx3g_test.v:27]
WARNING: [VRFC 10-1315] redeclaration of ansi port track_data_i is not allowed [f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/gtx3g_test.v:48]
INFO: [VRFC 10-311] analyzing module rst_generator
INFO: [VRFC 10-2263] Analyzing Verilog file "f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/prbs_chk.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module prbs_chk
INFO: [VRFC 10-2263] Analyzing Verilog file "f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/prbs_gen.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module prbs_gen
INFO: [VRFC 10-2263] Analyzing Verilog file "f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/simple_uart.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module simple_uart
INFO: [VRFC 10-2263] Analyzing Verilog file "f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sim_1/tb_gtx3g_test.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module tb_gtx3g_test
INFO: [VRFC 10-2263] Analyzing Verilog file "f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.sim/sim_1/behav/glbl.v" into library xil_defaultlib
INFO: [VRFC 10-311] analyzing module glbl
run_program: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 851.742 ; gain = 0.000
INFO: [USF-XSim-69] 'compile' step finished in '6' seconds
INFO: [USF-XSim-3] XSim::Elaborate design
INFO: [USF-XSim-61] Executing 'ELABORATE' step in 'f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.sim/sim_1/behav'
Vivado Simulator 2017.2
Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved.
Running: G:/Xilinx/Vivado/Vivado/2017.2/bin/unwrapped/win64.o/xelab.exe -wto 5ba44cec9b714e52b734f70e3b7f3445 --debug typical --relax --mt 2 -L xil_defaultlib -L unisims_ver -L unimacro_ver -L secureip -L xpm --snapshot tb_gtx3g_test_behav xil_defaultlib.tb_gtx3g_test xil_defaultlib.glbl -log elaborate.log
Using 2 slave threads.
Starting static elaboration
Completed static elaboration
Starting simulation data flow analysis
WARNING: [XSIM 43-4100] "f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/imports/example_design/gtx3g_exdes.v" Line 67. Module gtx3g_exdes has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/imports/example_design/support/gtx3g_support.v" Line 67. Module gtx3g_support(EXAMPLE_SIM_GTRESET_SPEEDUP="TRUE",STABLE_CLOCK_PERIOD=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/imports/example_design/support/gtx3g_gt_usrclk_source.v" Line 68. Module gtx3g_GT_USRCLK_SOURCE has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/verilog/src/unisims/IBUFDS_GTE2.v" Line 26. Module IBUFDS_GTE2 has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/verilog/src/unisims/BUFG.v" Line 27. Module BUFG has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/imports/example_design/support/gtx3g_common.v" Line 69. Module gtx3g_common(WRAPPER_SIM_GTRESET_SPEEDUP="TRUE",SIM_QPLLREFCLK_SEL=3'b010) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/verilog/src/unisims/GTXE2_COMMON.v" Line 25. Module GTXE2_COMMON(QPLL_CFG=27'b011010000000000111000001,QPLL_FBDIV=10'b010000000,QPLL_FBDIV_RATIO=1'b1,QPLL_REFCLK_DIV=1,SIM_QPLLREFCLK_SEL=3'b010,SIM_RESET_SPEEDUP="TRUE") has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 37. Module B_GTXE2_COMMON(BIAS_CFG=64'b01000000000000000000000000000001000000000000,COMMON_CFG=32'b0,QPLL_CFG=27'b011010000000000111000001,QPLL_CLKOUT_CFG=4'b0,QPLL_COARSE_FREQ_OVRD=6'b010000,QPLL_COARSE_FREQ_OVRD_EN=1'b0,QPLL_CP=10'b011111,QPLL_CP_MONITOR_EN=1'b0,QPLL_DMONITOR_SEL=1'b0,QPLL_FBDIV=10'b010000000,QPLL_FBDIV_MONITOR_EN=1'b0,QPLL_FBDIV_RATIO=1'b1,QPLL_INIT_CFG=24'b0110,QPLL_LOCK_CFG=16'b010000111101000,QPLL_LPF=4'b1111,QPLL_REFCLK_DIV=1,SIM_QPLLREFCLK_SEL=3'b010,SIM_RESET_SPEEDUP="TRUE",SIM_VERSION="4.0") has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 264. Module gtxe2_q443249(BIAS_CFG=64'b01000000000000000000000000000001000000000000,COMMON_CFG=32'b0,QPLL_CFG=27'b011010000000000111000001,QPLL_CLKOUT_CFG=4'b0,QPLL_COARSE_FREQ_OVRD=6'b010000,QPLL_COARSE_FREQ_OVRD_EN=1'b0,QPLL_CP=10'b011111,QPLL_CP_MONITOR_EN=1'b0,QPLL_DMONITOR_SEL=1'b0,QPLL_FBDIV=10'b010000000,QPLL_FBDIV_MONITOR_EN=1'b0,QPLL_FBDIV_RATIO=1'b1,QPLL_INIT_CFG=24'b0110,QPLL_LOCK_CFG=16'b010000111101000,QPLL_LPF=4'b1111,QPLL_REFCLK_DIV=1) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 162139. Module gtxe2_q625601 has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="DoNotCare",T_DELAY=0) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="DoNotCare",T_DELAY=0) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=0) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="DoNotCare",T_DELAY=0) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=0) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="DoNotCare",T_DELAY=0) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="DoNotCare",T_DELAY=0) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="DoNotCare",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="DoNotCare",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="DoNotCare",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="DoNotCare",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
WARNING: [XSIM 43-4100] "/wrk/2017.2/nightly/2017_06_15_1909853/data/secureip/gtxe2_common/gtxe2_common_002.vp" Line 161981. Module gtxe2_q900431(TIEOFF="0",T_DELAY=10) has a timescale but at least one module in design doesn't have timescale.
INFO: [Common 17-14] Message 'XSIM 43-4100' appears 50 times and further instances of the messages will be disabled. Use the Tcl command set_msg_config to change the current settings.
Completed simulation data flow analysis
Time Resolution for simulation is 1ps
Compiling module xil_defaultlib.rst_generator(cnt_num=10'b010000...
Compiling module xil_defaultlib.simple_uart_default
Compiling module unisims_ver.IBUFDS_GTE2
Compiling module unisims_ver.BUFG
Compiling module xil_defaultlib.gtx3g_GT_USRCLK_SOURCE
Compiling secureip modules ...
Compiling module unisims_ver.GTXE2_COMMON(QPLL_CFG=27'b011010...
Compiling module xil_defaultlib.gtx3g_common(WRAPPER_SIM_GTRESET...
Compiling module xil_defaultlib.gtx3g_common_reset(STABLE_CLOCK_...
Compiling secureip modules ...
Compiling module unisims_ver.GTXE2_CHANNEL(CHAN_BOND_MAX_SKEW...
Compiling module xil_defaultlib.gtx3g_GT(GT_SIM_GTRESET_SPEEDUP=...
Compiling module xil_defaultlib.gtx3g_multi_gt(WRAPPER_SIM_GTRES...
Compiling module unisims_ver.FDRE(INIT=1'b0)
Compiling module unisims_ver.FD(INIT=1'b0)
Compiling module xil_defaultlib.gtx3g_sync_block
Compiling module xil_defaultlib.gtx3g_TX_STARTUP_FSM(STABLE_CLOC...
Compiling module xil_defaultlib.gtx3g_RX_STARTUP_FSM(EXAMPLE_SIM...
Compiling module xil_defaultlib.gtx3g_sync_pulse
Compiling module xil_defaultlib.gtx3g_TX_MANUAL_PHASE_ALIGN(NUMB...
Compiling module xil_defaultlib.gtx3g_init_default
Compiling module xil_defaultlib.gtx3g
Compiling module xil_defaultlib.gtx3g_support(EXAMPLE_SIM_GTRESE...
Compiling module xil_defaultlib.prbs_gen(PRBS_INIT=16'b010000000...
Compiling module xil_defaultlib.gtx3g_GT_FRAME_GEN(WORDS_IN_BRAM...
Compiling module unisims_ver.FD
Compiling module xil_defaultlib.prbs_chk
Compiling module xil_defaultlib.gtx3g_GT_FRAME_CHECK(RX_DATA_WID...
Compiling module xil_defaultlib.gtx3g_exdes
Compiling module xil_defaultlib.gtx3g_test
Compiling module xil_defaultlib.tb_gtx3g_test
Compiling module xil_defaultlib.glbl
Built simulation snapshot tb_gtx3g_test_behav
****** Webtalk v2017.2 (64-bit)
**** SW Build 1909853 on Thu Jun 15 18:39:09 MDT 2017
**** IP Build 1909766 on Thu Jun 15 19:58:00 MDT 2017
** Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
source f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.sim/sim_1/behav/xsim.dir/tb_gtx3g_test_behav/webtalk/xsim_webtalk.tcl -notrace
INFO: [Common 17-186] 'f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.sim/sim_1/behav/xsim.dir/tb_gtx3g_test_behav/webtalk/usage_statistics_ext_xsim.xml' has been successfully sent to Xilinx on Sat Apr 28 19:49:02 2018. For additional details about this file, please refer to the WebTalk help file at G:/Xilinx/Vivado/Vivado/2017.2/doc/webtalk_introduction.html.
webtalk_transmit: Time (s): cpu = 00:00:00 ; elapsed = 00:00:09 . Memory (MB): peak = 61.145 ; gain = 0.137
INFO: [Common 17-206] Exiting Webtalk at Sat Apr 28 19:49:02 2018...
run_program: Time (s): cpu = 00:00:02 ; elapsed = 00:03:37 . Memory (MB): peak = 851.742 ; gain = 0.000
INFO: [USF-XSim-69] 'elaborate' step finished in '217' seconds
INFO: [USF-XSim-4] XSim::Simulate design
INFO: [USF-XSim-61] Executing 'SIMULATE' step in 'f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.sim/sim_1/behav'
INFO: [USF-XSim-98] *** Running xsim
with args "tb_gtx3g_test_behav -key {Behavioral:sim_1:Functional:tb_gtx3g_test} -tclbatch {tb_gtx3g_test.tcl} -log {simulate.log}"
INFO: [USF-XSim-8] Loading simulator feature
Vivado Simulator 2017.2
Time resolution is 1 ps
source tb_gtx3g_test.tcl
# set curr_wave [current_wave_config]
# if { [string length $curr_wave] == 0 } {
# if { [llength [get_objects]] > 0} {
# add_wave /
# set_property needs_save false [current_wave_config]
# } else {
# send_msg_id Add_Wave-1 WARNING "No top level signals found. Simulator will start without a wave window. If you want to open a wave window go to 'File->New Waveform Configuration' or type 'create_wave_config' in the TCL console."
# }
# }
# run 1000ns
xsim: Time (s): cpu = 00:00:07 ; elapsed = 00:00:23 . Memory (MB): peak = 851.742 ; gain = 0.000
INFO: [USF-XSim-96] XSim completed. Design snapshot 'tb_gtx3g_test_behav' loaded.
INFO: [USF-XSim-97] XSim simulation ran for 1000ns
launch_simulation: Time (s): cpu = 00:00:11 ; elapsed = 00:04:12 . Memory (MB): peak = 851.742 ; gain = 0.000
add_wave {{/tb_gtx3g_test/gtx3g_test_inst_0/gtx3g_exdes_i}}
add_wave {{/tb_gtx3g_test/gtx3g_test_inst_0/gtx3g_exdes_i/gt0_frame_gen}}
add_wave {{/tb_gtx3g_test/gtx3g_test_inst_0/gtx3g_exdes_i/gt0_frame_check}}
add_wave {{/tb_gtx3g_test/gtx3g_test_inst_0/gtx3g_exdes_i/gt0_frame_check/prbs_chk_inst_1}}
save_wave_config {F:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sim_1/tb_gtx3g_test_behav.wcfg}
add_files -fileset sim_1 -norecurse F:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sim_1/tb_gtx3g_test_behav.wcfg
set_property xsim.view F:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sim_1/tb_gtx3g_test_behav.wcfg [get_filesets sim_1]
run 110 us
run: Time (s): cpu = 00:01:14 ; elapsed = 00:10:55 . Memory (MB): peak = 860.984 ; gain = 6.152
save_wave_config {F:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sim_1/tb_gtx3g_test_behav.wcfg}
save_wave_config {F:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sim_1/tb_gtx3g_test_behav.wcfg}
save_wave_config {F:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sim_1/tb_gtx3g_test_behav.wcfg}
close_sim
INFO: [Simtcl 6-16] Simulation closed
close_sim: Time (s): cpu = 00:00:00 ; elapsed = 00:00:48 . Memory (MB): peak = 888.215 ; gain = 0.000
launch_runs synth_1 -jobs 2
INFO: [Vivado 12-4149] The synthesis checkpoint for IP 'f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/ip/gtx3g/gtx3g.xci' is already up-to-date
[Sat Apr 28 20:34:28 2018] Launched synth_1...
Run output will be captured here: f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.runs/synth_1/runme.log
launch_runs: Time (s): cpu = 00:00:02 ; elapsed = 00:00:16 . Memory (MB): peak = 988.207 ; gain = 99.992
reset_run synth_1
launch_runs synth_1 -jobs 2
INFO: [Vivado 12-4149] The synthesis checkpoint for IP 'f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/ip/gtx3g/gtx3g.xci' is already up-to-date
[Sat Apr 28 20:53:13 2018] Launched synth_1...
Run output will be captured here: f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.runs/synth_1/runme.log
open_run synth_1 -name synth_1
Design is defaulting to impl run constrset: constrs_1
Design is defaulting to synth run part: xc7z100iffg900-2L
INFO: [Project 1-454] Reading design checkpoint 'f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/ip/gtx3g/gtx3g.dcp' for cell 'gtx3g_exdes_i/gtx3g_support_i/gtx3g_init_i'
INFO: [Netlist 29-17] Analyzing 96 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 1 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2017.2
INFO: [Device 21-403] Loading part xc7z100iffg900-2L
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/ip/gtx3g/gtx3g.xdc] for cell 'gtx3g_exdes_i/gtx3g_support_i/gtx3g_init_i/inst'
Finished Parsing XDC File [f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/ip/gtx3g/gtx3g.xdc] for cell 'gtx3g_exdes_i/gtx3g_support_i/gtx3g_init_i/inst'
Parsing XDC File [f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/constrs_1/imports/example_design/gtx3g_exdes.xdc]
WARNING: [Vivado 12-507] No nets matched 'gtxaui3g_exdes_i/gtxaui3g_support_i/gt_usrclk_source/Q0_CLK1_GTREFCLK_OUT'. [f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/constrs_1/imports/example_design/gtx3g_exdes.xdc:138]
CRITICAL WARNING: [Common 17-55] 'set_property' expects at least one object. [f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/constrs_1/imports/example_design/gtx3g_exdes.xdc:138]
Resolution: If [get_<value>] was used to populate the object, check to make sure this command returns at least one valid object.
Finished Parsing XDC File [f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/constrs_1/imports/example_design/gtx3g_exdes.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
open_run: Time (s): cpu = 00:00:30 ; elapsed = 00:01:56 . Memory (MB): peak = 1504.891 ; gain = 493.598
reset_run synth_1
launch_runs synth_1 -jobs 2
INFO: [Vivado 12-4149] The synthesis checkpoint for IP 'f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/ip/gtx3g/gtx3g.xci' is already up-to-date
[Sat Apr 28 21:01:29 2018] Launched synth_1...
Run output will be captured here: f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.runs/synth_1/runme.log
close_design
close_design: Time (s): cpu = 00:00:03 ; elapsed = 00:00:11 . Memory (MB): peak = 1743.941 ; gain = 0.000
open_run synth_1 -name synth_1
Design is defaulting to impl run constrset: constrs_1
Design is defaulting to synth run part: xc7z100iffg900-2L
INFO: [Project 1-454] Reading design checkpoint 'f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/ip/gtx3g/gtx3g.dcp' for cell 'gtx3g_exdes_i/gtx3g_support_i/gtx3g_init_i'
INFO: [Netlist 29-17] Analyzing 96 Unisim elements for replacement
INFO: [Netlist 29-28] Unisim Transformation completed in 0 CPU seconds
INFO: [Project 1-479] Netlist was created with Vivado 2017.2
INFO: [Project 1-570] Preparing netlist for logic optimization
Parsing XDC File [f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/ip/gtx3g/gtx3g.xdc] for cell 'gtx3g_exdes_i/gtx3g_support_i/gtx3g_init_i/inst'
Finished Parsing XDC File [f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/ip/gtx3g/gtx3g.xdc] for cell 'gtx3g_exdes_i/gtx3g_support_i/gtx3g_init_i/inst'
Parsing XDC File [f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/constrs_1/imports/example_design/gtx3g_exdes.xdc]
Finished Parsing XDC File [f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/constrs_1/imports/example_design/gtx3g_exdes.xdc]
INFO: [Opt 31-138] Pushed 0 inverter(s) to 0 load pin(s).
INFO: [Project 1-111] Unisim Transformation Summary:
No Unisim elements were transformed.
open_run: Time (s): cpu = 00:00:12 ; elapsed = 00:00:20 . Memory (MB): peak = 1803.020 ; gain = 59.078
launch_runs impl_1 -to_step write_bitstream -jobs 2
INFO: [Vivado 12-4149] The synthesis checkpoint for IP 'f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.srcs/sources_1/ip/gtx3g/gtx3g.xci' is already up-to-date
Writing placer database...
Writing XDEF routing.
Writing XDEF routing logical nets.
Writing XDEF routing special nets.
Write XDEF Complete: Time (s): cpu = 00:00:01 ; elapsed = 00:00:02 . Memory (MB): peak = 1803.020 ; gain = 0.000
[Sat Apr 28 21:12:49 2018] Launched impl_1...
Run output will be captured here: f:/Programs/Verilog/FPGA_Group/test_gtx/gtx3g_ex/gtx3g_ex.runs/impl_1/runme.log
launch_runs: Time (s): cpu = 00:00:01 ; elapsed = 00:00:06 . Memory (MB): peak = 1803.020 ; gain = 0.000
close_design
exit
INFO: [Common 17-206] Exiting Vivado at Sat Apr 28 21:28:13 2018...