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Minisys-1_CPU by Ironprop SDU

MOOC 东南大学-计算机系统综合设计 Minisys-1

All Verilog files are in .src folder

  • minisys.v 顶层文件
  • control32.v 控制模块
  • control32_with_IO.v 带有IO功能的控制模块
  • dememory32.v ROM
  • executs32.v 执行模块
  • idecode32.v 译码模块
  • ifetc32.v 取指模块
  • memorio.v 选择ROM和IO模块
  • ioread.v IO
  • led.v LED_IO
  • switch.v switch_IO