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Update path to the reference SIM file for cross-talk tests (#130)
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BrieucF authored Nov 13, 2024
1 parent 150585f commit c80b0d6
Showing 1 changed file with 2 additions and 2 deletions.
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Expand Up @@ -52,8 +52,8 @@

# - general settings
#
inputfile = "https://fccsw.web.cern.ch/fccsw/filesForSimDigiReco/ALLEGRO/ALLEGRO_o1_v03/ALLEGRO_sim.root"
# note - this file probably contains the old ecal endcap segmentation so we disable the endcap digitisation later
inputfile = "https://fccsw.web.cern.ch/fccsw/filesForSimDigiReco/ALLEGRO/ALLEGRO_o1_v03/forTests/pythia_ee_z_qq_10evt_ALLEGRO_sim.root"
# note - this config tests cross talk which is not yet working for the endcap so we disable the endcap digitization
Nevts = 50 # -1 means all events
dumpGDML = False

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