TestBench: step() - use eval() to settle combinatorials before invert…

…ing clock
JimKnowler · Dec 30, 2020 · 9eb29b8 · 9eb29b8
1 parent 461885e
commit 9eb29b8
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Showing 2 changed files with 7 additions and 1 deletion.
diff --git a/gtestverilog/lib/TestBench.h b/gtestverilog/lib/TestBench.h
@@ -50,6 +50,10 @@ namespace gtestverilog {
 		/// @brief simulate a single half clock step
 		/// @note This will invert the current value on port 'i_clk'
 		void step() {
+			// evaluate core to allow combinatorial values to settle first
+			m_core->eval();
+
+			// invert clock and evaluate again
 			m_core->i_clk = (m_core->i_clk) ? 0 : 1;
 			m_core->eval();
 

diff --git a/gtestverilog/test/TestBench.test.cpp b/gtestverilog/test/TestBench.test.cpp
@@ -114,4 +114,6 @@ TEST(TestBench, ShouldSetClockPolarity1) {
     testBench.tick();
     ASSERT_EQ(1, core.i_clk);
 
-}
+}
+
+// TODO: test that combinatorial logic is evaluated before modifying clock during each step