TestBench: add support for clock polarity

JimKnowler · Dec 29, 2020 · c8df5ae · c8df5ae
1 parent 783f269
commit c8df5ae
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Showing 2 changed files with 52 additions and 6 deletions.
diff --git a/gtestverilog/lib/TestBench.h b/gtestverilog/lib/TestBench.h
@@ -15,11 +15,11 @@ namespace gtestverilog {
 		TestBench(void) {
 			m_core = std::make_unique<MODULE>();
 
-			m_stepCount = 0;
+			m_stepCount = 0;	
 
 			m_core->i_reset_n = 1;
-			m_core->i_clk = 0;
-			m_core->eval();
+
+			setClockPolarity(0);
 		}
 
 		~TestBench(void) {
@@ -38,11 +38,11 @@ namespace gtestverilog {
 		void tick(size_t numTicks = 1) {
 			for (size_t i=0; i<numTicks; i++) {
 				// rising edge
-				assert(m_core->i_clk == 0);
+				assert(m_core->i_clk == m_clockPolarity);
 				nextStep();
 
 				// falling edge
-				assert(m_core->i_clk == 1);
+				assert(m_core->i_clk != m_clockPolarity);
 				nextStep();
 			}
 		}
@@ -66,15 +66,26 @@ namespace gtestverilog {
 			return m_stepCount;
 		}
 
+		/// @brief set the polarity of i_clk
+		/// @value polarity the value of i_clk in IDLE state (either 0 or 1)
+		void setClockPolarity(int polarity) {
+			assert((polarity==1) || (polarity==0));
+			m_clockPolarity = polarity;
+
+			m_core->i_clk = m_clockPolarity;
+			m_core->eval();
+		}
+
 	protected:
 		virtual void onNextStep() {
 
 		}
 
 	private:
-		uint64_t    m_stepCount;
 		std::unique_ptr<MODULE>		m_core;
 
+		uint64_t    m_stepCount;
+		int 		m_clockPolarity;
 	};
 
 }
diff --git a/gtestverilog/test/TestBench.test.cpp b/gtestverilog/test/TestBench.test.cpp
@@ -79,4 +79,39 @@ TEST(TestBench, ShouldGetStepCount) {
 
     testBench.tick(3);
     ASSERT_EQ(8, testBench.stepCount());
+}
+
+TEST(TestBench, ShouldSetClockPolarity0) {
+    TestBench<TestCore> testBench;
+    auto& core = testBench.core();
+
+    testBench.setClockPolarity(0);
+    ASSERT_EQ(0, core.i_clk);
+
+    testBench.nextStep();
+    ASSERT_EQ(1, core.i_clk);
+
+    testBench.nextStep();
+    ASSERT_EQ(0, core.i_clk);
+
+    testBench.tick();
+    ASSERT_EQ(0, core.i_clk);
+}
+
+TEST(TestBench, ShouldSetClockPolarity1) {
+    TestBench<TestCore> testBench;
+    auto& core = testBench.core();
+
+    testBench.setClockPolarity(1);
+    ASSERT_EQ(1, core.i_clk);
+
+    testBench.nextStep();
+    ASSERT_EQ(0, core.i_clk);
+
+    testBench.nextStep();
+    ASSERT_EQ(1, core.i_clk);
+
+    testBench.tick();
+    ASSERT_EQ(1, core.i_clk);
+
 }