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Trace: truncate large traces when rendering them (including diffs for…
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… MatchTrace)
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JimKnowler committed Jan 3, 2022
1 parent 51b6ba0 commit da9d4ee
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Showing 3 changed files with 52 additions and 6 deletions.
12 changes: 12 additions & 0 deletions gtestverilog/example/Counter.test.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -75,5 +75,17 @@ TEST_F(Counter, ShouldSimulate) {
.port(i_simulate_combinatorial).signal( "01" ).repeat(11)
.port(i_simulate_sequential).signal( "10" ).repeat(11);

ASSERT_THAT(testBench.trace, MatchesTrace(traceExpected));
}

TEST_F(Counter, ShouldHandleLargeTraces) {
testBench.reset();
testBench.tick(1000);

const Trace traceExpected = TraceBuilder()
.port(i_clk).signal( "10" ).repeat(1001)
.port(i_simulate_combinatorial).signal( "01" ).repeat(1001)
.port(i_simulate_sequential).signal( "10" ).repeat(1001);

ASSERT_THAT(testBench.trace, MatchesTrace(traceExpected));
}
30 changes: 26 additions & 4 deletions gtestverilog/lib/MatchesTrace.cpp
Original file line number Diff line number Diff line change
@@ -1,7 +1,10 @@
#include "MatchesTrace.h"

#include <algorithm>

namespace gtestverilog {
namespace matches_trace {
const size_t kMaxTraceRenderSize = 80;

bool compare(const Trace& actual, const Trace& expected, ::testing::MatchResultListener& listener) {
bool hasMatched = true;
Expand Down Expand Up @@ -43,18 +46,37 @@ namespace matches_trace {
<< ConsoleColour().reset()
<< "\n";

std::vector<Step> stepsExpectedRender;
std::vector<Step> stepsActualRender;

size_t stepStart = 0;
size_t stepEnd = sizeActual;

if (sizeActual > kMaxTraceRenderSize) {
stepStart = (step > (kMaxTraceRenderSize/2)) ? step - (kMaxTraceRenderSize/2) : 0;
stepEnd = std::min(stepEnd, stepStart + kMaxTraceRenderSize);

listener << "Note: Diff truncated to steps " << stepStart << " to " << stepEnd << "\n";

stepsExpectedRender = std::vector<Step>(stepsExpected.begin() + stepStart, stepsExpected.begin() + stepEnd);
stepsActualRender = std::vector<Step>(stepsActual.begin() + stepStart, stepsActual.begin() + stepEnd);
} else {
stepsExpectedRender = stepsExpected;
stepsActualRender = stepsActual;
}

size_t maxPortLabelSize = expected.getMaxPortLabelSize();

listener << "\n";
listener << "Expected:";
Trace::renderPortDiff(*(listener.stream()), 'v', ConsoleColour::kGreen, maxPortLabelSize-9, portDesc, stepsExpected, stepsActual);
Trace::renderPortDiff(*(listener.stream()), 'v', ConsoleColour::kGreen, maxPortLabelSize-9, portDesc, stepsExpectedRender, stepsActualRender);

Trace::renderPort(*(listener.stream()), maxPortLabelSize, portDesc, stepsExpected);
Trace::renderPort(*(listener.stream()), maxPortLabelSize, portDesc, stepsExpectedRender);

listener << " Actual:";
Trace::renderPortDiff(*(listener.stream()), 'v', ConsoleColour::kRed, maxPortLabelSize-9, portDesc, stepsExpected, stepsActual);
Trace::renderPortDiff(*(listener.stream()), 'v', ConsoleColour::kRed, maxPortLabelSize-9, portDesc, stepsExpectedRender, stepsActualRender);

Trace::renderPort(*(listener.stream()), maxPortLabelSize, portDesc, stepsActual);
Trace::renderPort(*(listener.stream()), maxPortLabelSize, portDesc, stepsActualRender);
}

hasMatched = false;
Expand Down
16 changes: 14 additions & 2 deletions gtestverilog/lib/Trace.cpp
Original file line number Diff line number Diff line change
Expand Up @@ -2,8 +2,11 @@

#include <cstring>
#include <cmath>
#include <iostream>

namespace gtestverilog {
const size_t kMaxTraceRenderSize = 80;

Trace::Trace() {
}

Expand Down Expand Up @@ -137,10 +140,19 @@ namespace gtestverilog {
os << ConsoleColour().reset();

auto& steps = trace.getSteps();

std::vector<Step> stepsRender;

if (steps.size() <= kMaxTraceRenderSize) {
stepsRender = steps;
} else {
stepsRender = std::vector<Step>(steps.begin(), steps.begin() + kMaxTraceRenderSize);
os << "Note: Trace truncated to first " << kMaxTraceRenderSize << " steps\n";
}

size_t maxPortLabelSize = trace.getMaxPortLabelSize();

renderTimeline(os, maxPortLabelSize + 11, steps.size());
renderTimeline(os, maxPortLabelSize + 11, stepsRender.size());

for (uint32_t portId=0; portId<64; portId++) {
if (!trace.hasPort(portId)) {
Expand All @@ -149,7 +161,7 @@ namespace gtestverilog {

const PortDescription& portDesc = trace.getPortDescription(portId);

Trace::renderPort(os, maxPortLabelSize, portDesc, steps);
Trace::renderPort(os, maxPortLabelSize, portDesc, stepsRender);
}

return os;
Expand Down

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