Skip to content
View 0616ygh's full-sized avatar
😁
I may be slow to respond.
😁
I may be slow to respond.
  • Tsinghua University
  • Shenzhen
  • 07:39 (UTC +08:00)

Highlights

  • Pro

Block or report 0616ygh

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
0616ygh/README.md
  • 👋 Hi, I’m Guohua
  • 👀 I’m interested in computer architecture and open-source EDA
  • 🌱 I’m currently learning OpenLane and RISC-V
  • 📫 How to reach me : rios.y@rioslab.org

ß

Popular repositories Loading

  1. GreenRio2 GreenRio2 Public

    Verilog 7 7

  2. GreenRio2chip GreenRio2chip Public

    Verilog 3 2

  3. riosclass_template riosclass_template Public

    Verilog 1 13

  4. 0616ygh 0616ygh Public

    Config files for my GitHub profile.

    Jupyter Notebook

  5. rioschip rioschip Public

    Forked from b224hisl/rioschip

    Verilog

  6. sscs-ose-code-a-chip.github.io sscs-ose-code-a-chip.github.io Public

    Forked from sscs-ose/sscs-ose-code-a-chip.github.io

    IEEE Solid-State Circuits Society (SSCS) Open-Source Ecosystem (OSE) - “Code-a-Chip” Travel Grant Awards at ISSCC'23

    Jupyter Notebook 1