This respository provides training modules explaining how to design applications for the Intel Platform Acceleration Card (PAC).

Currently the repository includes explanations for writing RTL code, combined with C++, but will eventually be expanded to explain other design-entry methods including OpenCL, DPC++, OneAPI, and OpenVINO.

Training Modules

Here is an overview of the Intel PAC, along with the corresponding slides.

1. Register-transfer-level (RTL) training
   • Description: Explanation for how to develop RTL code for the Intel PAC
2. FPGA timing optimization
   • Description: Explanation for how to perform FPGA timing optimization.
3. SYCL Tutorial
   • Description: Tutorial on how to develop parallel applications using SYCL for FPGAs, GPUs, and CPUs.

DevCloud Instructions

• Explanation for how to register, connect, and use the DevCloud for these exercises.

• Quickstart Guide for Arria 10 PAC

• To clone this repository on the DevCloud, login after using the above instructions and then run:

    $ git clone https://github.com/ARC-Lab-UF/intel-training-modules.git