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Some tweaks to the SVE2p1 load and store intrinsics #359

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Some tweaks to the SVE2p1 load and store intrinsics #359

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e7dc5d6
Some tweaks to the SVE2p1 load and store intrinsics
rsandifo-arm Nov 6, 2024
8fc3a1b
Fix pointer types
rsandifo-arm Nov 13, 2024
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17 changes: 11 additions & 6 deletions main/acle.md
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Original file line number Diff line number Diff line change
Expand Up @@ -423,6 +423,7 @@ Armv8.4-A [[ARMARMv84]](#ARMARMv84). Support is added for the Dot Product intrin
* Fixed range of operand `o0` (too small) in AArch64 system register designations.
* Fixed SVE2.1 quadword gather load/scatter store intrinsics.
* Removed unnecessary Zd argument from `svcvtnb_mf8[_f32_x2]_fpm`.
* Removed extraneous `const` from SVE2.1 store intrinsics.

### References

Expand Down Expand Up @@ -9182,11 +9183,13 @@ Gather Load Quadword.
// _mf8, _bf16, _f16, _f32, _f64
svint8_t svld1q_gather[_u64base]_s8(svbool_t pg, svuint64_t zn);
svint8_t svld1q_gather[_u64base]_offset_s8(svbool_t pg, svuint64_t zn, int64_t offset);
svint8_t svld1q_gather_[s64]offset[_s8](svbool_t pg, const int8_t *base, svint64_t offset);
svint8_t svld1q_gather_[u64]offset[_s8](svbool_t pg, const int8_t *base, svuint64_t offset);

// Variants are also available for:
// _u16, _u32, _s32, _u64, _s64
// _bf16, _f16, _f32, _f64
svint16_t svld1q_gather_[s64]index[_s16](svbool_t pg, const int16_t *base, svint64_t index);
svint16_t svld1q_gather_[u64]index[_s16](svbool_t pg, const int16_t *base, svuint64_t index);
svint16_t svld1q_gather[_u64base]_index_s16(svbool_t pg, svuint64_t zn, int64_t index);
```
Expand Down Expand Up @@ -9256,14 +9259,14 @@ Contiguous store of single vector operand, truncating from quadword.
``` c
// Variants are also available for:
// _u32, _s32
void svst1wq[_f32](svbool_t, const float32_t *ptr, svfloat32_t data);
void svst1wq_vnum[_f32](svbool_t, const float32_t *ptr, int64_t vnum, svfloat32_t data);
void svst1wq[_f32](svbool_t, float32_t *ptr, svfloat32_t data);
void svst1wq_vnum[_f32](svbool_t, float32_t *ptr, int64_t vnum, svfloat32_t data);


// Variants are also available for:
// _u64, _s64
void svst1dq[_f64](svbool_t, const float64_t *ptr, svfloat64_t data);
void svst1dq_vnum[_f64](svbool_t, const float64_t *ptr, int64_t vnum, svfloat64_t data);
void svst1dq[_f64](svbool_t, float64_t *ptr, svfloat64_t data);
void svst1dq_vnum[_f64](svbool_t, float64_t *ptr, int64_t vnum, svfloat64_t data);
```

#### ST1Q
Expand All @@ -9276,12 +9279,14 @@ Scatter store quadwords.
// _mf8, _bf16, _f16, _f32, _f64
void svst1q_scatter[_u64base][_s8](svbool_t pg, svuint64_t zn, svint8_t data);
void svst1q_scatter[_u64base]_offset[_s8](svbool_t pg, svuint64_t zn, int64_t offset, svint8_t data);
void svst1q_scatter_[u64]offset[_s8](svbool_t pg, const uint8_t *base, svuint64_t offset, svint8_t data);
void svst1q_scatter_[s64]offset[_s8](svbool_t pg, int8_t *base, svint64_t offset, svint8_t data);
void svst1q_scatter_[u64]offset[_s8](svbool_t pg, int8_t *base, svuint64_t offset, svint8_t data);

// Variants are also available for:
// _u16, _u32, _s32, _u64, _s64
// _bf16, _f16, _f32, _f64
void svst1q_scatter_[u64]index[_s16](svbool_t pg, const int16_t *base, svuint64_t index, svint16_t data);
void svst1q_scatter_[s64]index[_s16](svbool_t pg, int16_t *base, svint64_t index, svint16_t data);
void svst1q_scatter_[u64]index[_s16](svbool_t pg, int16_t *base, svuint64_t index, svint16_t data);
void svst1q_scatter[_u64base]_index[_s16](svbool_t pg, svuint64_t zn, int64_t index, svint16_t data);
```

Expand Down