Merge pull request #223 from amrathesh/master

SBSA ACS Bug fixes

linux_app/sbsa-acs-app/sbsa_drv_intf.c

@@ -44,8 +44,6 @@ call_drv_get_status(unsigned long int *arg0, unsigned long int *arg1, unsigned l
 
     fd = fopen("/proc/sbsa", "r");
 
-    fseek(fd, 0, SEEK_SET);
-
     if (NULL == fd)
     {
         printf("fopen failed \n");
@@ -200,8 +198,6 @@ int read_from_proc_sbsa_msg() {
 
   fd = fopen("/proc/sbsa_msg", "r");
 
-  fseek(fd, 0, SEEK_SET);
-
   if (NULL == fd) {
     printf("fopen failed \n");
     return 1;

platform/pal_uefi/include/pal_uefi.h

@@ -35,6 +35,7 @@ extern UINT32 g_enable_module;
 #define PCIE_CAP_NOT_FOUND      0x10000010  /* The specified capability was not found */
 #define PCIE_UNKNOWN_RESPONSE   0xFFFFFFFF  /* Function not found or UR response from completer */
 
+#define NOT_IMPLEMENTED         0x4B1D  /* Feature or API by default unimplemented */
 
 typedef struct {
   UINT64   Arg0;

platform/pal_uefi/src/pal_exerciser.c

@@ -93,26 +93,6 @@ pal_exerciser_get_pcie_config_offset(UINT32 Bdf)
   return cfg_addr;
 }
 
-
-/**
-  @brief  This API returns if the device is a exerciser
-  @param  bdf - Bus/Device/Function
-  @return 1 - true 0 - false
-**/
-UINT32
-pal_is_bdf_exerciser(UINT32 bdf)
-{
-  UINT64 Ecam;
-  UINT32 vendor_dev_id;
-  Ecam = pal_pcie_get_mcfg_ecam();
-
-  vendor_dev_id = pal_mmio_read(Ecam + pal_exerciser_get_pcie_config_offset(bdf));
-  if (vendor_dev_id == EXERCISER_ID)
-     return 1;
-  else
-     return 0;
-}
-
 /**
   @brief This function triggers the DMA operation
 **/
@@ -511,3 +491,23 @@ pal_exerciser_get_data (
           return 1;
     }
 }
+
+/**
+  @brief   This API checks if the given Bdf is an exerciser
+  @param   Bdf         - Bdf of the device
+  @return  status      - 1 if bdf is exerciser
+                         0 if bdf is not exerciser
+**/
+UINT32
+pal_is_bdf_exerciser(UINT32 bdf)
+{
+  UINT64 Ecam;
+  UINT32 vendor_dev_id;
+  Ecam = pal_pcie_get_mcfg_ecam();
+
+  vendor_dev_id = pal_mmio_read(Ecam + pal_exerciser_get_pcie_config_offset(bdf));
+  if (vendor_dev_id == EXERCISER_ID)
+     return 1;
+  else
+     return 0;
+}

platform/pal_uefi/src/pal_pcie.c

@@ -213,6 +213,8 @@ pal_pcie_io_write_cfg(UINT32 Bdf, UINT32 offset, UINT32 data)
 
 /**
   @brief   This API checks the PCIe Hierarchy Supports P2P
+           This is platform dependent API.If the system supports peer 2 peer
+           traffic, return 0 else return 1
            1. Caller       -  Test Suite
   @return  1 - P2P feature not supported 0 - P2P feature supported
 **/
@@ -225,7 +227,7 @@ pal_pcie_p2p_support()
    * transactions is platform implementation specific
    */
 
-  return 0;
+  return NOT_IMPLEMENTED;
 }
 
 /**
@@ -275,14 +277,16 @@ pal_get_msi_vectors (
 
 /**
     @brief   Get legacy IRQ routing for a PCI device
-
+             This is Platform dependent API and needs to be filled
+             with legacy IRQ map for a pcie devices.
     @param   bus        PCI bus address
     @param   dev        PCI device address
     @param   fn         PCI function number
     @param   irq_map    pointer to IRQ map structure
 
     @return  irq_map    IRQ routing map
-    @return  status code
+    @return  status code If the device legacy irq map information is filled
+                         return 0, else returns NOT_IMPLEMENTED
 **/
 UINT32
 pal_pcie_get_legacy_irq_map (
@@ -293,7 +297,7 @@ pal_pcie_get_legacy_irq_map (
   PERIPHERAL_IRQ_MAP *IrqMap
   )
 {
-  return 1;
+  return NOT_IMPLEMENTED;
 }
 
 /* Place holder function. Need to be
@@ -311,8 +315,9 @@ pal_pcie_get_root_port_bdf (
 }
 
 /**
-  @brief   Platform dependent API checks the Address Translation
-           Cache Support for BDF
+  @brief   Checks the Address Translation Cache Support for BDF
+           Platform dependent API. Fill this with system ATC support
+           information for bdf's
            1. Caller       -  Test Suite
   @return  0 - ATC not supported 1 - ATC supported
 **/
@@ -324,7 +329,7 @@ pal_pcie_is_cache_present (
   UINT32 Fn
   )
 {
-  return 1;
+  return NOT_IMPLEMENTED;
 }
 
 /**

platform/pal_uefi/src/pal_pcie_enumeration.c

@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2016-2019, 2021 Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2016-2019, 2021-2022 Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -221,3 +221,22 @@ VOID pal_pcie_enumerate(VOID)
    * For uefi, enumeration is done during bootup
    * Hence, not implemented for uefi.*/
 }
+
+/**
+  @brief  This API is used as placeholder to check if the bdf
+          obtained is valid or not
+
+  @param  bdf
+  @return 0 if bdf is valid else 1
+**/
+UINT32
+pal_pcie_check_device_valid(UINT32 bdf)
+{
+
+  /*Add BDFs to this function if PCIe tests
+    need to be ignored for a BDF for any reason
+  */
+
+  return 0;
+}
+

test_pool/exerciser/test_e006.c

@@ -156,8 +156,16 @@ payload (void)
             val_gic_free_irq(e_intr_line, 0);
         }
    } else {
-        val_print (AVS_PRINT_ERR, "\n       Legacy interrupt mapping Read error for bdf: 0x%x", e_bdf);
-        test_fail++;
+        if (status == NOT_IMPLEMENTED) {
+           val_print(AVS_PRINT_DEBUG,
+           "\n       pal_pcie_get_legacy_irq_map unimplemented for bdf: 0x%x", e_bdf);
+            continue;
+        }
+        else {
+           val_print(AVS_PRINT_ERR, "\n       Legacy interrupt mapping Read error for bdf: 0x%x",
+                     e_bdf);
+           test_fail++;
+        }
    }
  }
 

test_pool/exerciser/test_e009.c

@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2019-2020, Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2019-2021, Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -40,6 +40,7 @@ payload(void)
   uint32_t reg_value;
   uint32_t instance;
   uint32_t fail_cnt;
+  uint32_t status;
   uint64_t header_type;
 
   fail_cnt = 0;
@@ -63,9 +64,21 @@ payload(void)
        * of the exerciser's root port. Exerciser should see this
        * request as a Type 0 Request.
        */
-      val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance);
+      status = val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance);
+      if (status == PCIE_CAP_NOT_FOUND)
+      {
+          val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 01));
+          return;
+      }
+
       val_pcie_read_cfg(e_bdf, TYPE01_VIDR, &reg_value);
-      val_exerciser_ops(STOP_TXN_MONITOR, CFG_READ, instance);
+      status = val_exerciser_ops(STOP_TXN_MONITOR, CFG_READ, instance);
+      if (status == PCIE_CAP_NOT_FOUND)
+      {
+          val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02));
+          return;
+      }
+
       val_exerciser_get_param(CFG_TXN_ATTRIBUTES, (uint64_t *)&header_type, 0, instance);
       if (header_type != TYPE0)
       {

test_pool/exerciser/test_e010.c

@@ -93,9 +93,12 @@ payload(void)
   uint32_t erp_rs_reg_value;
   uint32_t instance;
   uint32_t fail_cnt;
+  uint32_t test_skip;
+  uint32_t status;
   uint64_t header_type;
 
   fail_cnt = 0;
+  test_skip = 1;
   pe_index = val_pe_get_index_mpid(val_pe_get_mpid());
   instance = val_exerciser_get_info(EXERCISER_NUM_CARDS, 0);
 
@@ -147,23 +150,37 @@ payload(void)
        * of the exerciser. Exerciser should see this request as a
        * Type 1 Request.
        */
-      val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance);
+      status = val_exerciser_ops(START_TXN_MONITOR, CFG_READ, instance);
+      if (status == PCIE_CAP_NOT_FOUND)
+      {
+          goto restore;
+      }
+
       val_pcie_read_cfg(e_bdf, TYPE01_VIDR, &reg_value);
-      val_exerciser_ops(STOP_TXN_MONITOR, CFG_READ, instance);
+      status = val_exerciser_ops(STOP_TXN_MONITOR, CFG_READ, instance);
+      if (status == PCIE_CAP_NOT_FOUND)
+      {
+          goto restore;
+      }
+
+      test_skip = 0;
       val_exerciser_get_param(CFG_TXN_ATTRIBUTES, (uint64_t *)&header_type, 0, instance);
       if (header_type != TYPE1)
       {
           val_print(AVS_PRINT_ERR, "\n       BDF 0x%x Sub Bus Transaction failure", erp_bdf);
           fail_cnt++;
       }
 
+restore:
       /* Restore Exerciser rootport and it's right sibling subordinate bus registers */
       val_pcie_write_cfg(erp_bdf, TYPE1_PBN, erp_reg_value);
       if (rs_flag)
           val_pcie_write_cfg(erp_rs_bdf, TYPE1_PBN, erp_rs_reg_value);
   }
 
-  if (fail_cnt)
+  if (test_skip)
+      val_set_status(pe_index, RESULT_SKIP(g_sbsa_level, TEST_NUM, 02));
+  else if (fail_cnt)
       val_set_status(pe_index, RESULT_FAIL(g_sbsa_level, TEST_NUM, fail_cnt));
   else
       val_set_status(pe_index, RESULT_PASS(g_sbsa_level, TEST_NUM, 01));