Merge pull request #70 from edhay/release

v19.04_REL2.2: Add prebuilt image and update changelogs

README.md

@@ -17,7 +17,7 @@ A few tests are executed by running the SBSA ACS Linux application which in turn
 
 
 ## Release details
- - Code Quality: REL v2.1
+ - Code Quality: REL v2.2
  - The tests are written for version 5.0 of the SBSA specification.
  - The compliance suite is not a substitute for design verification.
  - To review the SBSA ACS logs, ARM licensees can contact ARM directly through their partner managers.
@@ -50,7 +50,7 @@ Prebuilt images for each release are available in the prebuilt_images folder of
     Before starting the ACS build, ensure that the following requirements are met.
 
 - Any mainstream Linux based OS distribution.
-- git clone [EDK2 tree](https://github.com/tianocore/edk2).
+- git clone the UDK2018 branch of [EDK2 tree](https://github.com/tianocore/edk2).
 - Install GCC 5.3 or later toolchain for Linux from [here](https://releases.linaro.org/components/toolchain/binaries/).
 - Install the build prerequisite packages to build EDK2. 
 Note: The details of the packages are beyond the scope of this document.

changelog.txt

@@ -1,3 +1,8 @@
+v19.04_REL2.2
+
+* SBSA: Support for baremetal templates with documentation.
+* SBSA: Big Endian Issue and ECAM bug fixes.
+
 v19.01_REL2.1
 
 * SBSA: Minor fixes in PCIe test cases 407, 412, 413, 415 and 416.

linux_app/sbsa-acs-app/include/sbsa_app.h

@@ -1,5 +1,5 @@
 /** @file
- * Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved.
+ * Copyright (c) 2016-2019, Arm Limited or its affiliates. All rights reserved.
  * SPDX-License-Identifier : Apache-2.0
 
  * Licensed under the Apache License, Version 2.0 (the "License");
@@ -21,7 +21,7 @@
 
 
 #define SBSA_APP_VERSION_MAJOR  2
-#define SBSA_APP_VERSION_MINOR  1
+#define SBSA_APP_VERSION_MINOR  2
 
 #include "sbsa_drv_intf.h"
 

platform/pal_baremetal/include/platform_override.h

@@ -0,0 +1,201 @@
+/** @file
+ * Copyright (c) 2019, Arm Limited or its affiliates. All rights reserved.
+ * SPDX-License-Identifier : Apache-2.0
+
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *  http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+**/
+
+
+/*
+ *Secure EL1 timer Flags, Non-Secure EL1 timer Flags, EL2 timer Flags,
+ * and Virtual timer Flags all can have the same definition as follows.
+ */
+#define INTERRUPT_IS_LEVEL_TRIGGERED 0x0
+#define INTERRUPT_IS_EDGE_TRIGGERED  0x1
+#define INTERRUPT_IS_ACTIVE_HIGH     0x0
+#define INTERRUPT_IS_ACTIVE_LOW      0x1
+
+#define TIMER_MODE      INTERRUPT_IS_LEVEL_TRIGGERED
+#define TIMER_POLARITY  INTERRUPT_IS_ACTIVE_LOW
+
+#define TIMER_IS_NON_SECURE 0x0
+#define TIMER_IS_SECURE     0x1
+
+#define TIMER_IS_ALWAYS_ON_INCAPABLE 0x0
+#define TIMER_IS_ALWAYS_ON_CAPABLE   0x1
+
+/* Timer platform config parameters */
+#define PLATFORM_OVERRIDE_S_EL1_TIMER_FLAGS     ((TIMER_POLARITY << 1) | (TIMER_MODE << 0))
+#define PLATFORM_OVERRIDE_NS_EL1_TIMER_FLAGS    ((TIMER_POLARITY << 1) | (TIMER_MODE << 0))
+#define PLATFORM_OVERRIDE_NS_EL2_TIMER_FLAGS    ((TIMER_POLARITY << 1) | (TIMER_MODE << 0))
+#define PLATFORM_OVERRIDE_VIRTUAL_TIMER_FLAGS   ((TIMER_POLARITY << 1) | (TIMER_MODE << 0))
+#define PLATFORM_OVERRIDE_S_EL1_TIMER_GSIV      0x1D
+#define PLATFORM_OVERRIDE_NS_EL1_TIMER_GSIV     0x1E
+#define PLATFORM_OVERRIDE_NS_EL2_TIMER_GSIV     0x1A
+#define PLATFORM_OVERRIDE_VIRTUAL_TIMER_GSIV    0x1B
+#define PLATFORM_OVERRIDE_EL2_VIR_TIMER_GSIV    28
+#define PLATFORM_OVERRIDE_PLATFORM_TIMER_COUNT  0x2
+
+#define PLATFORM_OVERRIDE_SYS_TIMER_TYPE        0x2001
+#define PLATFORM_OVERRIDE_TIMER_TYPE            PLATFORM_OVERRIDE_SYS_TIMER_TYPE
+#define PLATFORM_OVERRIDE_TIMER_COUNT           0x2
+#define PLATFORM_OVERRIDE_TIMER_CNTCTL_BASE     0x2a810000
+
+#define PLATFORM_OVERRIDE_TIMER_CNTBASE_0       0x2a830000
+#define PLATFORM_OVERRIDE_TIMER_CNTEL0BASE_0    0xFFFFFFFFFFFFFFFF
+#define PLATFORM_OVERRIDE_TIMER_GSIV_0          0x5c
+#define PLATFORM_OVERRIDE_TIMER_VIRT_GSIV_0     0x0
+#define PLATFORM_OVERRIDE_TIMER_PHY_FLAGS_0     0x0
+#define PLATFORM_OVERRIDE_TIMER_VIRT_FLAGS_0    0x0
+#define PLATFORM_OVERRIDE_TIMER_CMN_FLAGS_0     ((TIMER_IS_ALWAYS_ON_CAPABLE << 1) | (TIMER_IS_NON_SECURE << 0))
+#define PLATFORM_OVERRIDE_TIMER_FLAGS_0         ((PLATFORM_OVERRIDE_TIMER_CMN_FLAGS_0 << 16) | \
+                                                 (PLATFORM_OVERRIDE_TIMER_VIRT_FLAGS_0 << 8) | \
+                                                 (PLATFORM_OVERRIDE_TIMER_PHY_FLAGS_0))
+
+#define PLATFORM_OVERRIDE_TIMER_CNTBASE_1       0x2a820000
+#define PLATFORM_OVERRIDE_TIMER_CNTEL0BASE_1    0xFFFFFFFFFFFFFFFF
+#define PLATFORM_OVERRIDE_TIMER_GSIV_1          0x5B
+#define PLATFORM_OVERRIDE_TIMER_VIRT_GSIV_1     0x0
+#define PLATFORM_OVERRIDE_TIMER_PHY_FLAGS_1     0x0
+#define PLATFORM_OVERRIDE_TIMER_VIRT_FLAGS_1    0x0
+#define PLATFORM_OVERRIDE_TIMER_CMN_FLAGS_1     ((TIMER_IS_ALWAYS_ON_CAPABLE << 1) | (TIMER_IS_SECURE << 0))
+#define PLATFORM_OVERRIDE_TIMER_FLAGS_1         ((PLATFORM_OVERRIDE_TIMER_CMN_FLAGS_1 << 16) | \
+                                                 (PLATFORM_OVERRIDE_TIMER_VIRT_FLAGS_1 << 8) | \
+                                                 (PLATFORM_OVERRIDE_TIMER_PHY_FLAGS_1))
+
+/* Watchdog platform config parameters */
+#define WD_MODE     INTERRUPT_IS_LEVEL_TRIGGERED
+#define WD_POLARITY INTERRUPT_IS_ACTIVE_HIGH
+
+#define WD_IS_NON_SECURE 0x0
+#define WD_IS_SECURE     0x1
+
+#define PLATFORM_OVERRIDE_WD_TIMER_COUNT    0x1
+#define PLATFORM_OVERRIDE_WD_REFRESH_BASE   0x2A450000
+#define PLATFORM_OVERRIDE_WD_CTRL_BASE      0x2A440000
+#define PLATFORM_OVERRIDE_WD_GSIV           0x5D
+#define PLATFORM_OVERRIDE_WD_FLAGS          ((WD_IS_NON_SECURE << 2) | (WD_POLARITY << 1) | (WD_MODE << 0))
+
+
+/* GIC platform config parameters */
+#define PLATFORM_OVERRIDE_GIC_VERSION   0x00
+#define PLATFORM_OVERRIDE_CORE_COUNT    0x4
+#define PLATFORM_OVERRIDE_CLUSTER_COUNT 0x2
+#define PLATFORM_OVERRIDE_GICC_COUNT    (PLATFORM_OVERRIDE_CORE_COUNT * PLATFORM_OVERRIDE_CLUSTER_COUNT)
+#define PLATFORM_OVERRIDE_GICD_COUNT    0x1
+#define PLATFORM_OVERRIDE_GICRD_COUNT   (PLATFORM_OVERRIDE_CORE_COUNT * PLATFORM_OVERRIDE_CLUSTER_COUNT)
+#define PLATFORM_OVERRIDE_GICITS_COUNT  0x1
+#define PLATFORM_OVERRIDE_GICC_TYPE     0x1000
+#define PLATFORM_OVERRIDE_GICD_TYPE     0x1001
+#define PLATFORM_OVERRIDE_GICRD_TYPE    0x1002
+#define PLATFORM_OVERRIDE_GICITS_TYPE   0x1003
+#define PLATFORM_OVERRIDE_GICC_BASE     0x30000000
+#define PLATFORM_OVERRIDE_GICD_BASE     0x30000000
+#define PLATFORM_OVERRIDE_GICRD_BASE    0x300C0000
+#define PLATFORM_OVERRIDE_GICITS_BASE   0x30040000
+
+
+/* PE platform config paramaters */
+#define PLATFORM_OVERRIDE_PE_CNT        0x8
+#define PLATFORM_OVERRIDE_PE0_INDEX     0x0
+#define PLATFORM_OVERRIDE_PE0_MPIDR     0x0
+#define PLATFORM_OVERRIDE_PE0_PMU_GSIV  0x17
+#define PLATFORM_OVERRIDE_PE1_INDEX     0x1
+#define PLATFORM_OVERRIDE_PE1_MPIDR     0x100
+#define PLATFORM_OVERRIDE_PE1_PMU_GSIV  0x17
+#define PLATFORM_OVERRIDE_PE2_INDEX     0x2
+#define PLATFORM_OVERRIDE_PE2_MPIDR     0x200
+#define PLATFORM_OVERRIDE_PE2_PMU_GSIV  0x17
+#define PLATFORM_OVERRIDE_PE3_INDEX     0x3
+#define PLATFORM_OVERRIDE_PE3_MPIDR     0x300
+#define PLATFORM_OVERRIDE_PE3_PMU_GSIV  0x17
+#define PLATFORM_OVERRIDE_PE4_INDEX     0x4
+#define PLATFORM_OVERRIDE_PE4_MPIDR     0x10000
+#define PLATFORM_OVERRIDE_PE4_PMU_GSIV  0x17
+#define PLATFORM_OVERRIDE_PE5_INDEX     0x5
+#define PLATFORM_OVERRIDE_PE5_MPIDR     0x10100
+#define PLATFORM_OVERRIDE_PE5_PMU_GSIV  0x17
+#define PLATFORM_OVERRIDE_PE6_INDEX     0x6
+#define PLATFORM_OVERRIDE_PE6_MPIDR     0x10200
+#define PLATFORM_OVERRIDE_PE6_PMU_GSIV  0x17
+#define PLATFORM_OVERRIDE_PE7_INDEX     0x7
+#define PLATFORM_OVERRIDE_PE7_MPIDR     0x10300
+#define PLATFORM_OVERRIDE_PE7_PMU_GSIV  0x17
+
+typedef struct {
+  UINT32 pe_num;
+  UINT64 mpidr;
+  UINT32 pmu_gsiv;
+} PLATFORM_OVERRIDE_PE_INFO_ENTRY;
+
+typedef struct {
+  UINT32  num_of_pe;
+  PLATFORM_OVERRIDE_PE_INFO_ENTRY  pe_info[PLATFORM_OVERRIDE_PE_CNT];
+} PLATFORM_OVERRIDE_PE_INFO_TABLE;
+
+typedef struct {
+  UINT32 gic_version;
+  UINT32 num_gicc;
+  UINT32 num_gicd;
+  UINT32 num_gicrd;
+  UINT32 num_gicits;
+  UINT32 gicc_type;
+  UINT32 gicd_type;
+  UINT32 gicrd_type;
+  UINT32 gicits_type;
+  UINT64 gicc_base[PLATFORM_OVERRIDE_GICC_COUNT];
+  UINT64 gicd_base[PLATFORM_OVERRIDE_GICD_COUNT];
+  UINT64 gicrd_base[PLATFORM_OVERRIDE_GICRD_COUNT];
+  UINT64 gicits_base[PLATFORM_OVERRIDE_GICITS_COUNT];
+} PLATFORM_OVERRIDE_GIC_INFO_TABLE;
+
+typedef struct {
+  UINT32 s_el1_timer_flags;
+  UINT32 ns_el1_timer_flags;
+  UINT32 el2_timer_flags;
+  UINT32 s_el1_timer_gsiv;
+  UINT32 ns_el1_timer_gsiv;
+  UINT32 el2_timer_gsiv;
+  UINT32 virtual_timer_flags;
+  UINT32 virtual_timer_gsiv;
+  UINT32 el2_virt_timer_gsiv;
+  UINT32 num_platform_timer;
+} PLATFORM_OVERRIDE_TIMER_INFO_HDR;
+
+typedef struct {
+  UINT32 type;
+  UINT32 timer_count;
+  UINT64 block_cntl_base;
+  UINT64 GtCntBase[PLATFORM_OVERRIDE_TIMER_COUNT];
+  UINT64 GtCntEl0Base[PLATFORM_OVERRIDE_TIMER_COUNT];
+  UINT32 gsiv[PLATFORM_OVERRIDE_TIMER_COUNT];
+  UINT32 virt_gsiv[PLATFORM_OVERRIDE_TIMER_COUNT];
+  UINT32 flags[PLATFORM_OVERRIDE_TIMER_COUNT];
+} PLATFORM_OVERRIDE_TIMER_INFO_GTBLOCK;
+
+typedef struct {
+  PLATFORM_OVERRIDE_TIMER_INFO_HDR     header;
+  PLATFORM_OVERRIDE_TIMER_INFO_GTBLOCK gt_info;
+} PLATFORM_OVERRIDE_TIMER_INFO_TABLE;
+
+typedef struct {
+  UINT64 wd_ctrl_base;
+  UINT64 wd_refresh_base;
+  UINT32 wd_gsiv;
+  UINT32 wd_flags;
+} PLATFORM_OVERRIDE_WD_INFO_BLOCK;
+
+typedef struct {
+  UINT32 num_wd;
+  PLATFORM_OVERRIDE_WD_INFO_BLOCK  wd_info[PLATFORM_OVERRIDE_WD_TIMER_COUNT];
+} PLATFORM_OVERRIDE_WD_INFO_TABLE;

platform/pal_baremetal/src/AArch64/ArmSmc.S

@@ -0,0 +1,46 @@
+#/** @file
+# Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved.
+# SPDX-License-Identifier : Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#  http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#**/
+
+.text
+.align 3
+
+GCC_ASM_EXPORT(ArmCallSmc)
+
+ASM_PFX(ArmCallSmc):
+  // Push x0 on the stack - The stack must always be quad-word aligned
+  str   x0, [sp, #-16]!
+
+  // Load the SMC arguments values into the appropriate registers
+  ldp   x6, x7, [x0, #48]
+  ldp   x4, x5, [x0, #32]
+  ldp   x2, x3, [x0, #16]
+  ldp   x0, x1, [x0, #0]
+
+  smc   #0
+
+  // Pop the ARM_SMC_ARGS structure address from the stack into x9
+  ldr   x9, [sp], #16
+
+  // Store the SMC returned values into the ARM_SMC_ARGS structure.
+  // A SMC call can return up to 4 values - we do not need to store back x4-x7.
+  stp   x2, x3, [x9, #16]
+  stp   x0, x1, [x9, #0]
+
+  mov   x0, x9
+
+  ret

platform/pal_baremetal/src/AArch64/AvsTestInfra.S

@@ -0,0 +1,42 @@
+#/** @file
+# Copyright (c) 2016-2018, Arm Limited or its affiliates. All rights reserved.
+# SPDX-License-Identifier : Apache-2.0
+#
+# Licensed under the Apache License, Version 2.0 (the "License");
+# you may not use this file except in compliance with the License.
+# You may obtain a copy of the License at
+#
+#  http://www.apache.org/licenses/LICENSE-2.0
+#
+# Unless required by applicable law or agreed to in writing, software
+# distributed under the License is distributed on an "AS IS" BASIS,
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+# See the License for the specific language governing permissions and
+# limitations under the License.
+#
+#**/
+
+.text
+.align 3
+
+GCC_ASM_EXPORT(DataCacheCleanInvalidateVA)
+GCC_ASM_EXPORT(DataCacheInvalidateVA)
+GCC_ASM_EXPORT(DataCacheCleanVA)
+
+ASM_PFX(DataCacheCleanInvalidateVA):
+  dc  civac, x0
+  dsb sy
+  isb
+  ret
+
+ASM_PFX(DataCacheCleanVA):
+  dc  cvac, x0
+  dsb ish
+  isb
+  ret
+
+ASM_PFX(DataCacheInvalidateVA):
+  dc  ivac, x0
+  dsb ish
+  isb
+  ret