Skip to content
View AbijithT2003's full-sized avatar

Block or report AbijithT2003

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this user’s behavior. Learn more about reporting abuse.

Report abuse
AbijithT2003/README.md
  • 👋 Hi, I’m @AbijithT2003
  • 👀 I’m interested in c/cpp and verilog coding...
  • 🌱 I’m currently doing Bachelor in TECH in electronics and communication
  • 💞️ I’m looking to collaborate on literraly anything related to c/verilog
  • 📫 How to reach me stinsonb380@gmail.com
  • 😄 Pronouns: he/him
  • ⚡ Fun fact: fk pronouns

Popular repositories Loading

  1. AbijithT2003 AbijithT2003 Public

    Config files for my GitHub profile.

    Jupyter Notebook

  2. verilog-using-intel-quarts verilog-using-intel-quarts Public

    solution to problem statement on frequency scaling and Pulse Width Modulation on VERILOG(INTEL QUARTZ)

    Verilog