Skip to content
View AlPrime2k1's full-sized avatar

Highlights

  • Pro
Block or Report

Block or report AlPrime2k1

Block user

Prevent this user from interacting with your repositories and sending you notifications. Learn more about blocking users.

You must be logged in to block users.

Please don't include any personal information such as legal names or email addresses. Maximum 100 characters, markdown supported. This note will be visible to only you.
Report abuse

Contact GitHub support about this userโ€™s behavior. Learn more about reporting abuse.

Report abuse
AlPrime2k1/README.md

๐Ÿ’ซ About Me:

I'm Kirti

Iโ€™m currently working as a Verification Engineer.
๐ŸŒฑ Iโ€™m currently working on PCIe verification .
๐Ÿ’ฌ Ask me about Digital design, Verilog, SV, PCIe or anything random.

๐ŸŒ Socials:

LinkedIn Twitter


๐Ÿ“Š GitHub Stats:



โœ๏ธ Random Dev Quote

๐Ÿ’š From AlPrime2k1

Pinned Loading

  1. UVM UVM Public

    Repository containing various UVM based programs.

    SystemVerilog

  2. SystemVerilog SystemVerilog Public

    This repository consists of the files that i developed while learning SystemVerilog

    SystemVerilog

  3. APB-implementation-for-FPGA APB-implementation-for-FPGA Public

    This repository consists of all the related files for my B.Tech major project.

    Verilog 1

  4. Learning_CPP Learning_CPP Public

    Programs I created while learning C++

    C++

  5. Finite-State-Machines Finite-State-Machines Public

    Latest addition to REPO : Folder with vending machine design and TB including code coverage report

    HTML 2

  6. Sequential-Logic-Circuits Sequential-Logic-Circuits Public

    Verilog design and testbench files for Flip Flop, Counters, RAM, FIFO, Shift Registers and other sequential logic circuits

    Verilog 1 1