added exports for ports and output_ports

AlgebraicJulia · Oct 3, 2024 · 2a3d0da · 2a3d0da
1 parent f7a72aa
commit 2a3d0da
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diff --git a/src/dwd_dynam.jl b/src/dwd_dynam.jl
@@ -8,9 +8,8 @@ import ..UWDDynam: AbstractInterface, nstates, eval_dynamics, euler_approx, traj
 
 
 export AbstractMachine, ContinuousMachine, DiscreteMachine, DelayMachine, 
-InstantaneousContinuousMachine, InstantaneousDiscreteMachine, InstantaneousDelayMachine,
-nstates, ninputs, noutputs, eval_dynamics, readout, euler_approx, 
-dependency_pairs
+InstantaneousContinuousMachine, InstantaneousDiscreteMachine, InstantaneousDelayMachine, nstates, ninputs, noutputs, eval_dynamics, readout, euler_approx, 
+dependency_pairs, output_ports
 
 using Base.Iterators
 import Base: show, eltype, zero

diff --git a/src/uwd_dynam.jl b/src/uwd_dynam.jl
@@ -1,12 +1,11 @@
 module UWDDynam
 using Catlab
 
-
 using Catlab.WiringDiagrams.UndirectedWiringDiagrams: AbstractUWD
 import Catlab.WiringDiagrams: oapply, ports
 
 export AbstractResourceSharer, ContinuousResourceSharer, DelayResourceSharer, DiscreteResourceSharer,
-euler_approx, nstates, nports, portmap, portfunction, trajectory,
+euler_approx, nstates, nports, ports, portmap, portfunction, trajectory,
 eval_dynamics, eval_dynamics!, exposed_states, fills, induced_states
 
 using Base.Iterators