Created by: Angelo Jacobo
Date: August 22,2021
This project implements a pipelined Sobel Edge Detection using FPGA. This project is two-part:
- First is video processing. Video inputs(640x480@30FPS) are retrieved from OV7670 camera and is processed real-time via pipelined convolution module. Data are then stored and retrieved from SDRAM. Threshold value for edge detection is configurable via key[1:0]. key[2] is for alternating display between raw video and edge detected video. Full codes are on folder "src1".
- Second is image processing. Image inputs(640x480) are extracted from jpeg files using Matlab and is sent to FPGA serially. Python script is used to handle the UART protocol. Sobel edge detection is also done by the pipelined convolution module. Data are then stored and retrieved from SDRAM. Below are the sample images and its results. Full codes and instructions for running the scripts for Matlab and python are on folder "src2"
- top_module.v -> Combines the camera_interface, sdram_interface, and vga_interface modules.
key[1:0] for increasing/decreasing threshold value for Sobel edge detection
key[2] to change display between raw video or edge detected video - camera_interface.v -> Configures the register of OV7670 via SCCB protocol. Pixel data is retrieved from
the camera and then passed to asyn_fifo - sdram_interface.v -> Controls logic sequence for storing the pixel data retrieved from the camera_interface
and sobel_convolution, then sending it to the asyn_fifo connected
to vga_interface - vga_interface.v -> Passes the pixel data retrieved from sdram to the vga_core
- sobel_convolution.v -> Pipelined convolution logic. Pixel data from camera asyn_fifo are retrieved, processed,
and then sent to asyn_fifo of vga_interface per clock cycle - asyn_fifo.v -> FIFO with separate clock domains for read and write. Solves the clock domain crossing issue(see
image below) - i2c_top.v -> Bit-bang implementation of SCCB(which is very similar to i2c)
- sdram_controller.v -> Controller for storing to and retrieving data from SDRAM. Optimized to a memory
bandwidth of 316MB/s - vga_core.v -> VGA controller. Set at 640x480 @ 60fps
- top_module.ucf -> Constraint file for top_module.v
NOTE: dcm_24MHz.v , dcm_25MHz.v , and dcm_165MHz.v are PLL instantiations specific to Xilinx. Replace these files(and also the instantiation of these PLLs on the source code) when implementing this design to other FPGAs.
- top_module.v -> Combines the sdram_interface, vga_interface, and UART modules.
key[1:0] for increasing/decreasing threshold value for Sobel edge detection - sdram_interface.v -> Stores the pixel data processed by sobel_convolution module and
then sending it to the asyn_fifo connected to vga_interface - vga_interface.v -> Passes the pixel data retrieved from sdram to the vga_core
- uart.v -> UART driver. Set to a baud rate of 100_000 (115_200 produce data errors)
- sobel_convolution.v -> Pipelined convolution logic. Pixel data from uart are retrieved, processed, and then sent to
asyn_fifo of vga_interface per clock cycle - asyn_fifo.v -> FIFO with separate clock domains for read and write. Solves the clock domain crossing issue(see
image below) - sdram_controller.v -> Controller for storing to and retrieving data from SDRAM. Optimized to a memory
bandwidth of 316MB/s - vga_core.v -> VGA controller. Set at 640x480 @ 60fps
- top_module.ucf -> Constraint file for top_module.v
NOTE: dcm_24MHz.v , dcm_25MHz.v , and dcm_165MHz.v are PLL instantiations specific to Xilinx. Replace these files(and also the instantiation of these PLLs on the source code) when implementing this design to other FPGAs.
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