Student at Universidade Federal de Campina Grande. I am currently participating in a microelectronics training project in UFCG's Embedded Lab.
Pinned Loading
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julia_to_uvm_verification
julia_to_uvm_verification PublicForked from KelvinVale/julia_to_uvm_verification
It is a Julia script that generates VIP for interfaces, test file and top file in SystemVerilog.
Julia
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SystemVerilog_Playground
SystemVerilog_Playground PublicThis is where I put the SystemVerilog codes I made that I find the most interesting.
SystemVerilog 1
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riscv-formal
riscv-formal PublicForked from YosysHQ/riscv-formal
RISC-V Formal Verification Framework
Verilog
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FFT-Module-Verification
FFT-Module-Verification PublicThis is a UVM testbench for the functional verification of a FFT module.
SystemVerilog 2
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