A series of small projects for learning Verilog
Language
This repository contains different Verilog
projects that were created for learning purposes in Computer Architecture
Course in Noshirvani University of Technology
.
Each project contains a module and its test bench. Some projects contain different architectural implementations of the same module.
These projects were tested using Icarus Verilog
on Manjaro Linux.
- Icarus Verilog
- GTKWave
All modules and their test benches can be compiled and run with the Makefile
make MODULE=module_name
The Makefile will run the following commands:
iverilog -o module_name_out module_name.v module_name_tb.v
vvp module_name_tb
gtkwave module_name.vcd
Put the module that you want to test and its test bench in the same directory and run the Makefile with the module name to see the results.
- Adder:
- ALU:
- BUS:
- Counter:
- Finite State Machine:
- Seven Segment:
- Pipeline Project: