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implements AVR ABI and refines AVR targets
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open Bap_core_theory | ||
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val parent : Theory.target | ||
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val load : unit -> unit | ||
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type r8 | ||
type reg = r8 Theory.Bitv.t Theory.var | ||
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val parent : Theory.target | ||
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val tiny : Theory.target | ||
val mega : Theory.target | ||
val xmega : Theory.target | ||
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module Gcc : sig | ||
val args : reg list | ||
val rets : reg list | ||
val tiny : Theory.target | ||
val mega : Theory.target | ||
val xmega : Theory.target | ||
end |
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Original file line number | Diff line number | Diff line change |
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open Bap_main | ||
open Bap_core_theory | ||
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module AT = Bap_avr_target | ||
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module Abi = struct | ||
open Bap_c.Std | ||
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module Arg = C.Abi.Arg | ||
open Arg.Let | ||
open Arg.Syntax | ||
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let model = new C.Size.base `LP32 | ||
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let define t = | ||
C.Abi.define t model @@ fun _ {C.Type.Proto.return=r; args} -> | ||
let* iregs = Arg.Arena.create AT.Gcc.args in | ||
let* irets = Arg.Arena.create AT.Gcc.rets in | ||
let pass_via regs (_,t) = | ||
let open Arg in | ||
choice [ | ||
sequence [ | ||
align_even regs; | ||
registers regs t; | ||
]; | ||
sequence [ | ||
deplet regs; | ||
memory t; | ||
] | ||
] in | ||
let args = Arg.List.iter args ~f:(pass_via iregs) in | ||
let return = match r with | ||
| `Void -> None | ||
| r -> Some (pass_via irets ("",r)) in | ||
Arg.define ?return args | ||
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let setup () = | ||
List.iter define AT.Gcc.[tiny; mega; xmega] | ||
end | ||
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let main _ctxt = | ||
Bap_avr_target.load (); | ||
AT.load (); | ||
Abi.setup (); | ||
Ok () | ||
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let () = Bap_main.Extension.declare main | ||
~provides:[ | ||
"avr"; | ||
"lifter"; | ||
] | ||
~provides:["avr"; "lifter"; "disassembler"] |