Update patches to upsteram sail-riscv

riscv_patches/0001-Initialise-misa-for-CHERI-MCU-E-not-I-not-U-not-S-no.patch

@@ -1,35 +1,35 @@
-From d5a0048e5274cb1ce81030cfccc68060ce1183a4 Mon Sep 17 00:00:00 2001
+From 47c0bc46ee6152b89addb9432945b140bfe7fe3d Mon Sep 17 00:00:00 2001
 From: Robert Norton <ronorton@microsoft.com>
 Date: Mon, 31 Oct 2022 14:19:28 +0000
-Subject: [PATCH 01/10] Initialise misa for CHERI-MCU: E not I, not U, not S,
- not A.
+Subject: [PATCH 1/9] Initialise misa for CHERI-MCU: E not I, not U, not S, not
+ A.
 
 ---
  model/riscv_sys_control.sail | 9 +++++----
  1 file changed, 5 insertions(+), 4 deletions(-)
 
 diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail
-index 6204ae5..9e684d9 100644
+index 3830725..914caec 100644
 --- a/model/riscv_sys_control.sail
 +++ b/model/riscv_sys_control.sail
-@@ -552,12 +552,13 @@ function init_sys() -> unit = {
-   mhartid     = EXTZ(0b0);
+@@ -556,12 +556,13 @@ function init_sys() -> unit = {
+   mhartid     = zero_extend(0b0);
 
    misa->MXL() = arch_to_bits(if sizeof(xlen) == 32 then RV32 else RV64);
--  misa->A()   = 0b1;                            /* atomics */
-+  // misa->A()   = 0b1;                            /* atomics */
-   misa->C()   = bool_to_bits(sys_enable_rvc()); /* RVC */
--  misa->I()   = 0b1;                            /* base integer ISA */
-+  // misa->I()   = 0b1;                            /* base integer ISA */
+-  misa->A()   = 0b1;                             /* atomics */
++  // misa->A()   = 0b1;                             /* atomics */
+   misa->C()   = bool_to_bits(sys_enable_rvc());  /* RVC */
+-  misa->I()   = 0b1;                             /* base integer ISA */
++  // misa->I()   = 0b1;                             /* base integer ISA */
 +  misa->E()   = 0b1;
-   misa->M()   = 0b1;                            /* integer multiply/divide */
--  misa->U()   = 0b1;                            /* user-mode */
--  misa->S()   = 0b1;                            /* supervisor-mode */
-+  misa->U()   = 0b0;                            /* user-mode */
-+  misa->S()   = 0b0;                            /* supervisor-mode */
+   misa->M()   = 0b1;                             /* integer multiply/divide */
+-  misa->U()   = 0b1;                             /* user-mode */
+-  misa->S()   = 0b1;                             /* supervisor-mode */
++  misa->U()   = 0b0;                             /* user-mode */
++  misa->S()   = 0b0;                             /* supervisor-mode */
+   misa->V()   = bool_to_bits(sys_enable_vext()); /* vector extension */
 
    if   sys_enable_fdext() & sys_enable_zfinx()
-   then internal_error("F and Zfinx cannot both be enabled!");
 -- 
 2.39.2
 

riscv_patches/0002-Fix-handling-of-msatus.MIE-in-M-mode-only-case.patch

@@ -1,7 +1,7 @@
-From 8f054703175f4f1421b4638cfca50ba1e4e283bd Mon Sep 17 00:00:00 2001
+From 848c46be16d338cca297ca1e19527406f75befb5 Mon Sep 17 00:00:00 2001
 From: Robert Norton <ronorton@microsoft.com>
 Date: Mon, 31 Oct 2022 14:21:17 +0000
-Subject: [PATCH 02/10] Fix handling of msatus.MIE in M-mode only case.
+Subject: [PATCH 2/9] Fix handling of msatus.MIE in M-mode only case.
 
 Previously if neither user or supervisor mode are present
 dispatchInterrupt ignored mstatus.MIE leading to an infinite interrupt
@@ -11,12 +11,12 @@ loop.
  1 file changed, 8 insertions(+), 4 deletions(-)
 
 diff --git a/model/riscv_sys_control.sail b/model/riscv_sys_control.sail
-index 9e684d9..54a8daf 100644
+index 914caec..6b2aa42 100644
 --- a/model/riscv_sys_control.sail
 +++ b/model/riscv_sys_control.sail
-@@ -341,10 +341,14 @@ function dispatchInterrupt(priv : Privilege) -> option((InterruptType, Privilege
+@@ -345,10 +345,14 @@ function dispatchInterrupt(priv : Privilege) -> option((InterruptType, Privilege
     */
-   if (~ (haveUsrMode())) | ((~ (haveSupMode())) & (~ (haveNExt()))) then {
+   if not(haveUsrMode()) | (not(haveSupMode()) & not(haveNExt())) then {
      assert(priv == Machine, "invalid current privilege");
 -    let enabled_pending = mip.bits() & mie.bits();
 -    match findPendingInterrupt(enabled_pending) {

riscv_patches/0003-Crash-if-reading-or-writing-upper-16-registers-TODO-.patch

@@ -1,18 +1,18 @@
-From 6970cd7d361b44f9ca52a5abd4a0e6c4ac550482 Mon Sep 17 00:00:00 2001
+From d2f3d2cefbe1257a6f7eb5d1aa82a8eccab066e8 Mon Sep 17 00:00:00 2001
 From: Robert Norton <ronorton@microsoft.com>
 Date: Mon, 31 Oct 2022 14:49:45 +0000
-Subject: [PATCH 03/10] Crash if reading or writing upper 16 registers: TODO
- this should really be reserved instruction trap.
+Subject: [PATCH 3/9] Crash if reading or writing upper 16 registers: TODO this
+ should really be reserved instruction trap.
 
 ---
  model/riscv_regs.sail | 32 --------------------------------
  1 file changed, 32 deletions(-)
 
 diff --git a/model/riscv_regs.sail b/model/riscv_regs.sail
-index a65c6c5..d9ef101 100644
+index 15e7613..4ff7871 100644
 --- a/model/riscv_regs.sail
 +++ b/model/riscv_regs.sail
-@@ -128,22 +128,6 @@ function rX r = {
+@@ -130,22 +130,6 @@ function rX r = {
        13 => x13,
        14 => x14,
        15 => x15,
@@ -35,7 +35,7 @@ index a65c6c5..d9ef101 100644
        _  => {assert(false, "invalid register number"); zero_reg}
      };
    regval_from_reg(v)
-@@ -181,22 +165,6 @@ function wX (r, in_v) = {
+@@ -183,22 +167,6 @@ function wX (r, in_v) = {
      13 => x13 = v,
      14 => x14 = v,
      15 => x15 = v,

riscv_patches/0004-Add-very-basic-output-only-MMIO-UART-for-terminal-ou.patch

@@ -1,8 +1,7 @@
-From 812e68c5745c8e220c3ba67374a6d889a6c9ec63 Mon Sep 17 00:00:00 2001
+From a64a1c55a35e95d8303156e52cca02d48a9e161e Mon Sep 17 00:00:00 2001
 From: Robert Norton <ronorton@microsoft.com>
 Date: Mon, 31 Oct 2022 14:59:58 +0000
-Subject: [PATCH 04/10] Add very basic output-only MMIO UART for terminal
- output.
+Subject: [PATCH 4/9] Add very basic output-only MMIO UART for terminal output.
 
 Mapped at 0x10000100 to match flute, with address hardcoded in a
 similar way to CLINT. Should make this configurable.
@@ -15,12 +14,12 @@ similar way to CLINT. Should make this configurable.
  5 files changed, 95 insertions(+), 4 deletions(-)
 
 diff --git a/c_emulator/riscv_platform.c b/c_emulator/riscv_platform.c
-index 2572dbc..7a257fc 100644
+index fbd63fa..71600d2 100644
 --- a/c_emulator/riscv_platform.c
 +++ b/c_emulator/riscv_platform.c
-@@ -58,6 +58,13 @@ mach_bits plat_clint_base(unit u)
- mach_bits plat_clint_size(unit u)
- { return rv_clint_size; }
+@@ -108,6 +108,13 @@ mach_bits plat_clint_size(unit u)
+   return rv_clint_size;
+ }
 
 +mach_bits plat_uart_base(unit u)
 +{ return rv_uart_base; }
@@ -33,10 +32,10 @@ index 2572dbc..7a257fc 100644
  {
    reservation = addr;
 diff --git a/c_emulator/riscv_platform.h b/c_emulator/riscv_platform.h
-index 5335a90..a9b98bb 100644
+index 4b6541f..9a3f25a 100644
 --- a/c_emulator/riscv_platform.h
 +++ b/c_emulator/riscv_platform.h
-@@ -25,6 +25,9 @@ mach_bits plat_get_16_random_bits();
+@@ -27,6 +27,9 @@ mach_bits plat_get_16_random_bits();
  mach_bits plat_clint_base(unit);
  mach_bits plat_clint_size(unit);
 
@@ -47,10 +46,10 @@ index 5335a90..a9b98bb 100644
  unit load_reservation(mach_bits);
  bool match_reservation(mach_bits);
 diff --git a/c_emulator/riscv_platform_impl.c b/c_emulator/riscv_platform_impl.c
-index b1504a7..9aca0b7 100644
+index 15ff8ad..75f77e9 100644
 --- a/c_emulator/riscv_platform_impl.c
 +++ b/c_emulator/riscv_platform_impl.c
-@@ -37,6 +37,9 @@ uint64_t rv_16_random_bits(void) {
+@@ -40,6 +40,9 @@ uint64_t rv_16_random_bits(void)
  uint64_t rv_clint_base = UINT64_C(0x2000000);
  uint64_t rv_clint_size = UINT64_C(0xc0000);
 
@@ -61,10 +60,10 @@ index b1504a7..9aca0b7 100644
  uint64_t rv_insns_per_tick = UINT64_C(100);
 
 diff --git a/c_emulator/riscv_platform_impl.h b/c_emulator/riscv_platform_impl.h
-index 165fb94..34edd1e 100644
+index e5c562a..0a6329e 100644
 --- a/c_emulator/riscv_platform_impl.h
 +++ b/c_emulator/riscv_platform_impl.h
-@@ -29,6 +29,9 @@ extern uint64_t rv_16_random_bits(void);
+@@ -32,6 +32,9 @@ extern uint64_t rv_16_random_bits(void);
  extern uint64_t rv_clint_base;
  extern uint64_t rv_clint_size;
 
@@ -75,10 +74,10 @@ index 165fb94..34edd1e 100644
  extern uint64_t rv_insns_per_tick;
 
 diff --git a/model/riscv_platform.sail b/model/riscv_platform.sail
-index ea27f48..eb8946d 100644
+index 579a118..71960c2 100644
 --- a/model/riscv_platform.sail
 +++ b/model/riscv_platform.sail
-@@ -124,6 +124,10 @@ val plat_rom_size   = {ocaml: "Platform.rom_size", interpreter: "Platform.rom_si
+@@ -126,6 +126,10 @@ val plat_rom_size   = {ocaml: "Platform.rom_size", interpreter: "Platform.rom_si
  val plat_clint_base = {ocaml: "Platform.clint_base", interpreter: "Platform.clint_base", c: "plat_clint_base", lem: "plat_clint_base"} : unit -> xlenbits
  val plat_clint_size = {ocaml: "Platform.clint_size", interpreter: "Platform.clint_size", c: "plat_clint_size", lem: "plat_clint_size"} : unit -> xlenbits
 
@@ -89,7 +88,7 @@ index ea27f48..eb8946d 100644
  /* Location of HTIF ports */
  val plat_htif_tohost = {ocaml: "Platform.htif_tohost", c: "plat_htif_tohost", lem: "plat_htif_tohost"} : unit -> xlenbits
  function plat_htif_tohost () = to_bits(sizeof(xlen), elf_tohost ())
-@@ -183,6 +187,18 @@ function within_htif_writable forall 'n, 0 < 'n <= max_mem_access . (addr : xlen
+@@ -185,6 +189,18 @@ function within_htif_writable forall 'n, 0 < 'n <= max_mem_access . (addr : xlen
  function within_htif_readable forall 'n, 0 < 'n <= max_mem_access . (addr : xlenbits, width : atom('n)) -> bool =
      plat_htif_tohost() == addr | (plat_htif_tohost() + 4 == addr & width == 4)
 
@@ -108,7 +107,7 @@ index ea27f48..eb8946d 100644
  /* CLINT (Core Local Interruptor), based on Spike. */
 
  val plat_insns_per_tick = {ocaml: "Platform.insns_per_tick", interpreter: "Platform.insns_per_tick", c: "plat_insns_per_tick", lem: "plat_insns_per_tick"} : unit -> int
-@@ -452,20 +468,77 @@ function htif_tick() = {
+@@ -454,20 +470,77 @@ function htif_tick() = {
  /* Top-level MMIO dispatch */
  $ifndef RVFI_DII
  function within_mmio_readable forall 'n, 0 < 'n <= max_mem_access . (addr : xlenbits, width : atom('n)) -> bool =
@@ -143,7 +142,7 @@ index ea27f48..eb8946d 100644
 +function uart_load(t, addr, width) = {
 +  let offset = addr - plat_uart_base();
 +  /* We only support reading the status register, which always indicates ready to write output */
-+  if offset == UART_OFFSET_LINE_STATUS & ('n == 4)
++  if offset == zero_extend(UART_OFFSET_LINE_STATUS) & ('n == 4)
 +  then {
 +    let result = 0b100000; /* TXBufEmpty always */
 +    if   get_config_print_platform()
@@ -164,12 +163,12 @@ index ea27f48..eb8946d 100644
 +function uart_store(addr, width, data) = {
 +  let offset = addr - plat_uart_base();
 +  /* only support writing to the data register for output, ignore other writes */
-+  if offset == UART_OFFSET_DATA & ('n == 8 | 'n == 4) then {
++  if offset == zero_extend(UART_OFFSET_DATA) & ('n == 8 | 'n == 4) then {
 +    if   get_config_print_platform()
 +    then print_platform("uart[" ^ BitStr(offset) ^ "] <- " ^ BitStr(data));
 +    if UART_DLAB == bitzero then plat_term_write(data[7..0]);
 +    MemValue(true)
-+  } else if offset == UART_OFFSET_LINE_CTL & ('n == 8 | 'n == 4) then {
++  } else if offset == zero_extend(UART_OFFSET_LINE_CTL) & ('n == 8 | 'n == 4) then {
 +    if   get_config_print_platform()
 +    then print_platform("uart[" ^ BitStr(offset) ^ "] <- " ^ BitStr(data));
 +    UART_DLAB = data[7];
@@ -189,7 +188,7 @@ index ea27f48..eb8946d 100644
    then clint_load(t, paddr, width)
    else if within_htif_readable(paddr, width) & (1 <= 'n)
    then htif_load(t, paddr, width)
-@@ -476,7 +549,9 @@ function mmio_read forall 'n, 0 < 'n <= max_mem_access . (t : AccessType(ext_acc
+@@ -478,7 +551,9 @@ function mmio_read forall 'n, 0 < 'n <= max_mem_access . (t : AccessType(ext_acc
    }
 
  function mmio_write forall 'n, 0 <'n <= max_mem_access . (paddr : xlenbits, width : atom('n), data: bits(8 * 'n)) -> MemoryOpResult(bool) =

riscv_patches/0005-riscv_sim-Add-command-line-arguments-to-enable-or-di.patch

@@ -1,7 +1,7 @@
-From 41c00661efdc44da5f606941e833ba0395c51e5c Mon Sep 17 00:00:00 2001
+From a03f2b539f022bd64cdec1baba6bd0c8dba22846 Mon Sep 17 00:00:00 2001
 From: Robert Norton <ronorton@microsoft.com>
 Date: Mon, 31 Oct 2022 14:46:27 +0000
-Subject: [PATCH 05/10] riscv_sim: Add command line arguments to enable or
+Subject: [PATCH 5/9] riscv_sim: Add command line arguments to enable or
  disable use of boot ROM.
 
 This adds command line arguments --boot-rom and --no-boot-rom to
@@ -13,14 +13,14 @@ the simulator just sets the initial PC to the entry point.  For
 backwards compatibility the default is to use the boot-rom unless
 NO_BOOT_ROM is defined during compilation.
 ---
- c_emulator/riscv_sim.c | 20 ++++++++++++++++++--
- 1 file changed, 18 insertions(+), 2 deletions(-)
+ c_emulator/riscv_sim.c | 17 +++++++++++++++--
+ 1 file changed, 15 insertions(+), 2 deletions(-)
 
 diff --git a/c_emulator/riscv_sim.c b/c_emulator/riscv_sim.c
-index 5ad83e9..787714e 100644
+index 13d1653..08aa211 100644
 --- a/c_emulator/riscv_sim.c
 +++ b/c_emulator/riscv_sim.c
-@@ -76,6 +76,13 @@ bool config_print_reg = true;
+@@ -83,6 +83,13 @@ bool config_print_reg = true;
  bool config_print_mem_access = true;
  bool config_print_platform = true;
  bool config_print_rvfi = false;
@@ -32,42 +32,42 @@ index 5ad83e9..787714e 100644
 +#endif
 +;
 
- void set_config_print(char *var, bool val) {
-   if (var == NULL || strcmp("all", var) == 0) {
-@@ -131,6 +138,8 @@ static struct option options[] = {
-   {"no-trace",                    optional_argument, 0, 'V'},
-   {"inst-limit",                  required_argument, 0, 'l'},
-   {"enable-zfinx",                no_argument,       0, 'x'},
-+  {"boot-rom",                    no_argument, &config_use_boot_rom, true},
-+  {"no-boot-rom",                 no_argument, &config_use_boot_rom, false},
+ void set_config_print(char *var, bool val)
+ {
+@@ -142,6 +149,8 @@ static struct option options[] = {
+     {"inst-limit",                  required_argument, 0, 'l'                     },
+     {"enable-zfinx",                no_argument,       0, 'x'                     },
+     {"enable-writable-fiom",        no_argument,       0, OPT_ENABLE_WRITABLE_FIOM},
++    {"boot-rom",                    no_argument, &config_use_boot_rom, true},
++    {"no-boot-rom",                 no_argument, &config_use_boot_rom, false},
  #ifdef SAILCOV
-   {"sailcov-file",                required_argument, 0, 'c'},
+     {"sailcov-file",                required_argument, 0, 'c'                     },
  #endif
-@@ -146,7 +155,10 @@ static void print_usage(const char *argv0, int ec)
+@@ -156,10 +165,10 @@ static void print_usage(const char *argv0, int ec)
  #endif
    struct option *opt = options;
    while (opt->name) {
--    fprintf(stdout, "\t -%c\t --%s\n", (char)opt->val, opt->name);
+-    if (isprint(opt->val))
 +    if (opt->flag == NULL)
-+      fprintf(stdout, "\t -%c\t --%s\n", (char)opt->val, opt->name);
-+    else
+       fprintf(stdout, "\t -%c\t --%s\n", (char)opt->val, opt->name);
+     else
+-      fprintf(stdout, "\t   \t --%s\n", opt->name);
 +      fprintf(stdout, "\t\t --%s\n", opt->name);
      opt++;
    }
    exit(ec);
-@@ -551,7 +563,11 @@ void init_sail(uint64_t elf_entry)
+@@ -601,7 +610,11 @@ void init_sail(uint64_t elf_entry)
      zPC = elf_entry;
    } else
  #endif
--  init_sail_reset_vector(elf_entry);
 +  if (config_use_boot_rom) {
-+    init_sail_reset_vector(elf_entry);
+     init_sail_reset_vector(elf_entry);
 +  } else {
 +    zPC = elf_entry;
 +  }
 
    // this is probably unnecessary now; remove
-   if (!rv_enable_rvc) z_set_Misa_C(&zmisa, 0);
+   if (!rv_enable_rvc)
 -- 
 2.39.2