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CHERI ISAv10 is now a work-in-progress #124

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CHERI ISAv10 is now a work-in-progress #124

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36 changes: 18 additions & 18 deletions abstract.tex
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\section*{Abstract}

This technical report describes CHERI ISAv9, the ninth version of the
This technical report describes CHERI ISAv10, the tenth version of the
CHERI architecture
being developed by SRI International and the University of Cambridge.
This design captures thirteen years of research, development, experimentation,
Expand Down Expand Up @@ -51,20 +51,20 @@ \section*{Abstract}
processing (which are concentrations of both complex and historically
vulnerability-prone code exposed to untrustworthy data sources).

CHERI ISAv9 is a substantial enhancement to prior ISA versions.
CHERI-RISC-V has replaced CHERI-MIPS as the primary reference
platform, and CHERI-MIPS has been removed from the specification.
CHERI architectures now always use merged register files where
existing general-purpose registers are extended to support
capabilities.
CHERI architectures have adopted two design decisions from Arm
Morello: 1) CHERI architectures now clear tags rather than raising
exceptions if an instruction attempts a non-monotonic modification
of a capability; and 2) \DDC{} and \PCC{} no longer relocate legacy
memory accesses by default.
CHERI-RISC-V has received numerous updates to serve as a better
baseline for an upstream standard proposal including a more mature
definition of compressed instructions in capability mode.
CHERI-x86-64 now includes details of extensions to existing x86
instructions and proposed new instructions in a separate ISA
reference chapter along with various other updates.
CHERI ISAv10 is a substantial enhancement to prior ISA versions.
% CHERI-RISC-V has replaced CHERI-MIPS as the primary reference
% platform, and CHERI-MIPS has been removed from the specification.
% CHERI architectures now always use merged register files where
% existing general-purpose registers are extended to support
% capabilities.
% CHERI architectures have adopted two design decisions from Arm
% Morello: 1) CHERI architectures now clear tags rather than raising
% exceptions if an instruction attempts a non-monotonic modification
% of a capability; and 2) \DDC{} and \PCC{} no longer relocate legacy
% memory accesses by default.
% CHERI-RISC-V has received numerous updates to serve as a better
% baseline for an upstream standard proposal including a more mature
% definition of compressed instructions in capability mode.
% CHERI-x86-64 now includes details of extensions to existing x86
% instructions and proposed new instructions in a separate ISA
% reference chapter along with various other updates.
6 changes: 6 additions & 0 deletions app-versions-10-0.tex
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This version of the \textit{CHERI Instruction-Set Architecture} is a full
release of the Version 10 specification:

\begin{itemize}
\item \textbf{TBD}
\end{itemize}
3 changes: 3 additions & 0 deletions app-versions.tex
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Expand Up @@ -1077,4 +1077,7 @@ \section{Detailed CHERI ISA Version Change History}
\item[9.0]
\input{app-versions-9-0}

\item[10.0]
\input{app-versions-10-0}

\end{description}
8 changes: 4 additions & 4 deletions chap-intro.tex
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Expand Up @@ -660,22 +660,22 @@ \section{CHERI ISA Version History}
\label{table:intro-cheri-isa-versions}
\end{table}

This is the nineth version of the CHERI ISA specification document.
This is the tenth version of the CHERI ISA specification document.
A high-level summary of CHERI ISA versions and their corresponding
contributions can be found in Table~\ref{table:intro-cheri-isa-versions}.
A much more detailed version summary and complete change log can be found in
Appendix~\ref{app:versions}.
A more narrative exploration of the research and development cycle leading to
our current specification can be found in Chapter~\ref{chap:research}.

\subsection{Changes in CHERI ISA 9.0}
\subsection{Changes in CHERI ISA 10.0}

\input{app-versions-9-0}
\input{app-versions-10-0}

\section{Experimental Features}
\label{sec:intro:experimental}

\rwnote{Ensure this is updated for ISAv9}
\rwnote{Ensure this is updated for ISAv10}

Appendix~\ref{app:experimental} describes a number of experimental features
that extend CHERI with new functionality.
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4 changes: 2 additions & 2 deletions cheri-architecture.tex
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Expand Up @@ -18,7 +18,7 @@
\begin{document}
\title{Capability Hardware Enhanced RISC Instructions: \\
\smallskip CHERI Instruction-Set Architecture \\
{\large Version 9}}
{\large Version 10 - DRAFT}}
\author{
\parbox{\linewidth}{\centering%
Robert~N.~M.~Watson,
Expand Down Expand Up @@ -53,7 +53,7 @@
\\
SRI International, University of Cambridge, and Arm Limited
}
\date{22nd September 2023}
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% \date{22nd September 2023}

%% CL tech-report format provides its own cover page
\ifdefined\trformat
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