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28 Open 57 Closed
28 Open 57 Closed
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Issues list

Instruction tracing can use wrong encoding mode
#255 opened Jun 18, 2024 by arichardson
@qwattash
User mode uses inefficient structures to store information on pages user-mode
#240 opened Oct 16, 2023 by kwitaszczyk
gdb stub support for CHERI-RISC-V 'special' registers enhancement
#238 opened Sep 5, 2023 by tmarkettos
@bsdjhb
'savevm' monitor command crashes QEMU.
#205 opened Oct 7, 2022 by jacobbramley
5
Morello 'rrlen' instruction is implemented incorrectly.
#197 opened May 30, 2022 by jacobbramley
2
Should warn when starting smbd > 4.13 enhancement help wanted
#196 opened Mar 20, 2022 by arichardson
QEMU/RISC-V: CHERI+MTE (ISAv8 appendix) Research
#186 opened Oct 22, 2021 by gvnn3
@rmn30
2
Virtio-GPU support for QEMU 2D/3D graphics Engineering
#185 opened Oct 22, 2021 by gvnn3 2022 Q2 Release
@bukinr
2
CheriABI Linux user mode for Morello Engineering user-mode
#174 opened Oct 12, 2021 by gvnn3 2022 Q3 Release
@trasz
Ctrl-C in interactive morello-purecap session hits assertion and brings down QEMU.
#173 opened Oct 12, 2021 by jacobbramley
1
2
Crash in QEMU monitor
#165 opened Sep 13, 2021 by huhrenfeldt
Core dump support for CheriABI CHERI-RISC-V BSD user mode. enhancement user-mode
#164 opened Sep 7, 2021 by kwitaszczyk
@kwitaszczyk
CheriABI CheriBSD user mode for CHERI-RISC-V Engineering packages Issues related to package building user-mode
#163 opened Sep 1, 2021 by kwitaszczyk
12 of 28 tasks
@kwitaszczyk
1
{fork,vfork,exec}-events gdb extensions in the user-mode. enhancement user-mode
#162 opened Sep 1, 2021 by kwitaszczyk
@kwitaszczyk
Differences between QEMU and FVP on Morello
#151 opened Jun 17, 2021 by brettferdosi
@LawrenceEsswood
10
Instruction logging should print current instruction disassembly before breakpoints
#106 opened Jun 2, 2020 by arichardson
@qwattash
Move icount benchmarking code to instruction logging. enhancement
#104 opened May 29, 2020 by qwattash
@qwattash
RISCV appears to crash when running with -icount auto bug RISCV
#100 opened May 16, 2020 by qwattash
@qwattash
Rewrite tagged memory implementation
#89 opened Mar 27, 2020 by arichardson
Bounds+permission checks for branches and jumps RISCV
#88 opened Mar 27, 2020 by arichardson
Should add a GDB test for CHERI registers
#83 opened Mar 19, 2020 by arichardson
-DCHERI_UNALIGNED doesn't trap on accesses across cacheline boundaries enhancement
#69 opened Mar 21, 2018 by arichardson
Add a trap on invalid physical address access enhancement help wanted
#64 opened Jan 2, 2018 by arichardson
@staceyson @qwattash
Time behaves funny bug
#55 opened Oct 5, 2017 by trasz
2
Time is slow bug
#54 opened Oct 5, 2017 by trasz
10
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