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Merge branch 'ChibiOS:chibios-21.11.x' into chibios-21.11.x-wb
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@itarze
itarze authored Jun 14, 2024
2 parents dc625dd + 5621625 commit 17c34f2
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Showing 51 changed files with 5,889 additions and 1,947 deletions.
128 changes: 89 additions & 39 deletions demos/ES32/FS026/cfg/mcuconf.h
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Expand Up @@ -17,6 +17,8 @@
#ifndef MCUCONF_H
#define MCUCONF_H

#define ES32_FS026_MCUCONF

/**
* @name Internal clock sources
* @{
Expand All @@ -28,22 +30,64 @@
/*
* HAL driver system settings.
*/
#define ES32_NO_INIT FALSE
#define ES32_MHSI_ENABLED TRUE
#define ES32_FHSI_ENABLED FALSE
#define ES32_LSI_ENABLED FALSE
#define ES32_HSE_ENABLED TRUE
#define ES32_LSE_ENABLED FALSE
#define ES32_PLL_ENABLED TRUE
#define ES32_MAINCLKSRC ES32_MAINCLKSRC_PLL
#define ES32_HSE_STATE ANCTL_HSECR0_HSEON
#define ES32_PLLSRC ES32_PLLSRC_HSE
#define ES32_PLLDIV_VALUE 2
#define ES32_PLLMUL_VALUE 12 // The allowed range is 12,16,20,24.
#define ES32_HPRE 1
#define ES32_PPRE1 1
#define ES32_PPRE2 1
#define ES32_USBPRE ES32_USBPRE_DIV1P5
#define ES32_NO_INIT FALSE

/*system_clk select
MD_RCU_SW_SYSCLK_HRC = HRC selected as system clock
MD_RCU_SW_SYSCLK_HOSC = HOSC selected as system clock
MD_RCU_SW_SYSCLK_PLL0 = PLL0 selected as system clock
MD_RCU_SW_SYSCLK_HRC48 = HRC48 selected as system clock
*/
#define ES32_SYSCLK_SOURSE_SELECT MD_RCU_SW_SYSCLK_PLL0

/*external clk config*/
#define ES32_HOSC_CLK_EN FALSE
#define ES32_HOSC_CLK_FREQ 8

/*pll clk config
MD_RCU_PLLSRC_HRC = HRC selected as PLL reference clock
MD_RCU_PLLSRC_HOSC = HOSC selected as PLL reference clock
MD_RCU_PLLSRC_HRC48 = HRC48 selected as PLL reference clock
MD_RCU_PLLCLK_PASS = 0
MD_RCU_PLLCLK_4M = 4000000
MD_RCU_PLLCLK_8M = 8000000
MD_RCU_PLLCLK_12M = 12000000
MD_RCU_PLLCLK_16M = 16000000
MD_RCU_PLLCLK_24M = 24000000
MD_RCU_PLLCLK_32M = 32000000
MD_RCU_PLLCLK_36M = 36000000
MD_RCU_PLLCLK_40M = 40000000
MD_RCU_PLLCLK_48M = 48000000
MD_RCU_PLLCLK_64M = 64000000
MD_RCU_PLLCLK_72M = 72000000
*/
#define ES32_PLL_CLK_EN TRUE
#define ES32_PLL_SOURSE_SELECT MD_RCU_PLLSRC_HRC48
#define ES32_PLL_CLK_FREQ MD_RCU_PLLCLK_72M

/*bus clk config
MD_RCU_HPRE_SYSCLK_DIV_1 = SYSCLK not divided
MD_RCU_HPRE_SYSCLK_DIV_2 = SYSCLK divided by 2
MD_RCU_HPRE_SYSCLK_DIV_4 = SYSCLK divided by 4
MD_RCU_HPRE_SYSCLK_DIV_8 = SYSCLK divided by 8
MD_RCU_HPRE_SYSCLK_DIV_16 = SYSCLK divided by 16
MD_RCU_HPRE_SYSCLK_DIV_64 = SYSCLK divided by 64
MD_RCU_HPRE_SYSCLK_DIV_128 = SYSCLK divided by 128
MD_RCU_HPRE_SYSCLK_DIV_256 = SYSCLK divided by 256
MD_RCU_HPRE_SYSCLK_DIV_512 = @brief SYSCLK divided by 512
MD_RCU_PPRE_HCLK_DIV_1 = HCLK not divided
MD_RCU_PPRE_HCLK_DIV_2 = HCLK divided by 2
MD_RCU_PPRE_HCLK_DIV_4 = HCLK divided by 4
MD_RCU_PPRE_HCLK_DIV_8 = HCLK divided by 8
MD_RCU_PPRE_HCLK_DIV_16 = HCLK divided by 16
*/
#define ES32_BUS_DIV_HPRE MD_RCU_HPRE_SYSCLK_DIV_1
#define ES32_BUS_DIV_PPRE MD_RCU_PPRE_HCLK_DIV_1

/*
* EXTI driver system settings.
Expand Down Expand Up @@ -88,15 +132,24 @@
/*
* PWM driver system settings.
*/
#define ES32_PWM_USE_ADVANCED FALSE
#define ES32_PWM_USE_TIM1 FALSE
#define ES32_PWM_USE_TIM2 FALSE
#define ES32_PWM_USE_TIM3 FALSE
#define ES32_PWM_USE_TIM4 FALSE
#define ES32_PWM_TIM1_IRQ_PRIORITY 7
#define ES32_PWM_TIM2_IRQ_PRIORITY 7
#define ES32_PWM_TIM3_IRQ_PRIORITY 7
#define ES32_PWM_TIM4_IRQ_PRIORITY 7
#define ES32_PWM_USE_AD16C4T1 TRUE
#define ES32_PWM_USE_GP32C4T1 TRUE
#define ES32_PWM_USE_GP16C4T1 TRUE
#define ES32_PWM_USE_GP16C4T2 TRUE
#define ES32_PWM_USE_GP16C4T3 TRUE
#define ES32_PWM_USE_GP16C2T1 TRUE
#define ES32_PWM_USE_GP16C2T2 TRUE
#define ES32_PWM_USE_GP16C2T3 TRUE
#define ES32_PWM_USE_GP16C2T4 TRUE
#define ES32_PWM_AD16C4T1_IRQ_PRIORITY 7
#define ES32_PWM_GP32C4T1_IRQ_PRIORITY 7
#define ES32_PWM_GP16C4T1_IRQ_PRIORITY 7
#define ES32_PWM_GP16C4T2_IRQ_PRIORITY 7
#define ES32_PWM_GP16C4T3_IRQ_PRIORITY 7
#define ES32_PWM_GP16C2T1_IRQ_PRIORITY 7
#define ES32_PWM_GP16C2T2_IRQ_PRIORITY 7
#define ES32_PWM_GP16C2T3_IRQ_PRIORITY 7
#define ES32_PWM_GP16C2T4_IRQ_PRIORITY 7

/*
* I2C driver system settings.
Expand All @@ -110,24 +163,20 @@
/*
* SERIAL driver system settings.
*/
#define ES32_SERIAL_USE_UART1 FALSE
#define ES32_SERIAL_USE_UART2 FALSE
#define ES32_SERIAL_USE_UART3 FALSE
#define ES32_SERIAL_USART1_PRIORITY 12
#define ES32_SERIAL_USART2_PRIORITY 12
#define ES32_SERIAL_USART3_PRIORITY 12
#define ES32_SERIAL_USE_UART1 TRUE
#define ES32_SERIAL_USE_UART2 TRUE
#define ES32_SERIAL_USE_UART3 TRUE
#define ES32_SERIAL_USE_UART4 TRUE
#define ES32_SERIAL_USART1_PRIORITY 7
#define ES32_SERIAL_USART1_PRIORITY 7
#define ES32_SERIAL_USART1_PRIORITY 7
#define ES32_SERIAL_USART1_PRIORITY 7

/*
* SPI driver system settings.
*/
#define ES32_SPI_USE_QSPI FALSE
#define ES32_SPI_USE_SPIM2 FALSE
#define ES32_SPI_USE_SPIS1 FALSE
#define ES32_SPI_USE_SPIS2 FALSE
#define ES32_SPI_QSPI_IRQ_PRIORITY 10
#define ES32_SPI_SPIM2_IRQ_PRIORITY 10
#define ES32_SPI_SPIS1_IRQ_PRIORITY 10
#define ES32_SPI_SPIS2_IRQ_PRIORITY 10
#define ES32_SPI_USE_SPI1 TRUE
#define ES32_SPI_USE_SPI2 TRUE

/*
* ST driver system settings.
Expand All @@ -151,6 +200,7 @@
#define ES32_USB_USE_USB1 TRUE
#define ES32_USB_USB1_IRQ_PRIORITY 13
#define ES32_USB_HOST_WAKEUP_DURATION 10
#define ES32_USE_USB_SOF_TRIM_HRC48 TRUE

/*
* ADC driver system settings.
Expand Down
2 changes: 1 addition & 1 deletion os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415.h
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Expand Up @@ -204,4 +204,4 @@ typedef enum {ERROR = 0, SUCCESS = !ERROR} error_status;
* @}
*/

/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/
/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/
11 changes: 3 additions & 8 deletions os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415cx.h
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Expand Up @@ -470,10 +470,7 @@ typedef struct
{
__IO uint32_t EVTOUT; /*!< IOMUX Event output control register, Address offset: 0x00 */
__IO uint32_t REMAP; /*!< IOMUX remap register 1, Address offset: 0x04 */
__IO uint32_t EXINTC1; /*!< IOMUX external interrupt config register 1, Address offset: 0x08 */
__IO uint32_t EXINTC2; /*!< IOMUX external interrupt config register 2, Address offset: 0x0C */
__IO uint32_t EXINTC3; /*!< IOMUX external interrupt config register 3, Address offset: 0x10 */
__IO uint32_t EXINTC4; /*!< IOMUX external interrupt config register 4, Address offset: 0x14 */
__IO uint32_t EXINTC[4]; /*!< IOMUX external interrupt config register, Address offset: 0x08 ~ 0x14 */
uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
__IO uint32_t REMAP2; /*!< IOMUX remap register 2, Address offset: 0x1C */
__IO uint32_t REMAP3; /*!< IOMUX remap register 3, Address offset: 0x20 */
Expand Down Expand Up @@ -696,9 +693,7 @@ typedef struct

#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */
#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
#define UID1_BASE 0x1FFFF7E8U /*!< Unique device ID register 1 base address */
#define UID2_BASE 0x1FFFF7ECU /*!< Unique device ID register 2 base address */
#define UID3_BASE 0x1FFFF7F0U /*!< Unique device ID register 3 base address */
#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
#define USD_BASE 0x1FFFF800U /*!< FLASH User System Data base address */

#define DEBUG_BASE 0xE0042000U /*!< Debug MCU registers base address */
Expand Down Expand Up @@ -10494,4 +10489,4 @@ typedef struct

#endif /* __AT32F415Cx_H */

/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/
/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/
11 changes: 3 additions & 8 deletions os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415kx.h
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Expand Up @@ -469,10 +469,7 @@ typedef struct
{
__IO uint32_t EVTOUT; /*!< IOMUX Event output control register, Address offset: 0x00 */
__IO uint32_t REMAP; /*!< IOMUX remap register 1, Address offset: 0x04 */
__IO uint32_t EXINTC1; /*!< IOMUX external interrupt config register 1, Address offset: 0x08 */
__IO uint32_t EXINTC2; /*!< IOMUX external interrupt config register 2, Address offset: 0x0C */
__IO uint32_t EXINTC3; /*!< IOMUX external interrupt config register 3, Address offset: 0x10 */
__IO uint32_t EXINTC4; /*!< IOMUX external interrupt config register 4, Address offset: 0x14 */
__IO uint32_t EXINTC[4]; /*!< IOMUX external interrupt config register, Address offset: 0x08 ~ 0x14 */
uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
__IO uint32_t REMAP2; /*!< IOMUX remap register 2, Address offset: 0x1C */
__IO uint32_t REMAP3; /*!< IOMUX remap register 3, Address offset: 0x20 */
Expand Down Expand Up @@ -694,9 +691,7 @@ typedef struct

#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */
#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
#define UID1_BASE 0x1FFFF7E8U /*!< Unique device ID register 1 base address */
#define UID2_BASE 0x1FFFF7ECU /*!< Unique device ID register 2 base address */
#define UID3_BASE 0x1FFFF7F0U /*!< Unique device ID register 3 base address */
#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
#define USD_BASE 0x1FFFF800U /*!< FLASH User System Data base address */

#define DEBUG_BASE 0xE0042000U /*!< Debug MCU registers base address */
Expand Down Expand Up @@ -10444,4 +10439,4 @@ typedef struct

#endif /* __AT32F415Kx_H */

/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/
/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/
11 changes: 3 additions & 8 deletions os/common/ext/CMSIS/ArteryTek/AT32F415/at32f415rx.h
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Original file line number Diff line number Diff line change
Expand Up @@ -472,10 +472,7 @@ typedef struct
{
__IO uint32_t EVTOUT; /*!< IOMUX Event output control register, Address offset: 0x00 */
__IO uint32_t REMAP; /*!< IOMUX remap register 1, Address offset: 0x04 */
__IO uint32_t EXINTC1; /*!< IOMUX external interrupt config register 1, Address offset: 0x08 */
__IO uint32_t EXINTC2; /*!< IOMUX external interrupt config register 2, Address offset: 0x0C */
__IO uint32_t EXINTC3; /*!< IOMUX external interrupt config register 3, Address offset: 0x10 */
__IO uint32_t EXINTC4; /*!< IOMUX external interrupt config register 4, Address offset: 0x14 */
__IO uint32_t EXINTC[4]; /*!< IOMUX external interrupt config register, Address offset: 0x08 ~ 0x14 */
uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
__IO uint32_t REMAP2; /*!< IOMUX remap register 2, Address offset: 0x1C */
__IO uint32_t REMAP3; /*!< IOMUX remap register 3, Address offset: 0x20 */
Expand Down Expand Up @@ -700,9 +697,7 @@ typedef struct

#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000U) /*!< FLASH registers base address */
#define FLASHSIZE_BASE 0x1FFFF7E0U /*!< FLASH Size register base address */
#define UID1_BASE 0x1FFFF7E8U /*!< Unique device ID register 1 base address */
#define UID2_BASE 0x1FFFF7ECU /*!< Unique device ID register 2 base address */
#define UID3_BASE 0x1FFFF7F0U /*!< Unique device ID register 3 base address */
#define UID_BASE 0x1FFFF7E8U /*!< Unique device ID register base address */
#define USD_BASE 0x1FFFF800U /*!< FLASH User System Data base address */

#define DEBUG_BASE 0xE0042000U /*!< Debug MCU registers base address */
Expand Down Expand Up @@ -10537,4 +10532,4 @@ typedef struct

#endif /* __AT32F415Rx_H */

/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/
/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/
2 changes: 1 addition & 1 deletion os/common/ext/CMSIS/ArteryTek/AT32F415/system_at32f415.h
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Expand Up @@ -109,4 +109,4 @@ extern void SystemCoreClockUpdate(void);
* @}
*/

/*********************** (C) COPYRIGHT Artery Technologies *****END OF FILE****/
/*********************** (C) COPYRIGHT Artery Technology *****END OF FILE****/
3 changes: 2 additions & 1 deletion os/common/ext/CMSIS/ES32/FS026/md/md_adc.c
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Expand Up @@ -161,7 +161,7 @@ void md_adc_sequence_conversion(ADC_TypeDef *ADCx, md_adc_initial *ADC_InitStruc
ErrorStatus md_adc_software_calibration(ADC_TypeDef *ADCx, md_adc_initial *ADC_InitStruct)
{
//ADC input APB clock 12MHz
uint8_t clkdiv;
uint8_t clkdiv = 1;
uint16_t adc_data_1 = 0;
uint16_t adc_data_15 = 0;

Expand Down Expand Up @@ -277,6 +277,7 @@ ErrorStatus md_adc_optionbyte_calibration(ADC_TypeDef *ADCx, md_adc_initial *ADC
md_adc_enable_adcpower(ADCx);
md_adc_set_gain_factor(ADCx, adc_gain);
md_adc_set_offset_factor(ADCx, adc_offset);
(void)ADC_InitStruct;
return SUCCESS;
}

Expand Down
2 changes: 0 additions & 2 deletions os/common/ext/CMSIS/ES32/FS026/md/md_i2c.c
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Original file line number Diff line number Diff line change
Expand Up @@ -337,8 +337,6 @@ void md_i2c_slave_receive(I2C_TypeDef *I2Cx, uint32_t Num, uint8_t *rxbuf)

while (!(md_i2c_is_active_flag_busy(I2Cx)));

printf("I2C1->STAT:%x\r\n", I2C1->STAT);

while (Num > 0)
{
while (!(md_i2c_is_active_flag_rxne(I2Cx)));
Expand Down
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