Advanced Synthesis and STA Using Design Compiler and SkyWater130nm Library

This repository mainly focuses on the Synthesis part in the ASIC design flow. Here you will hget an idea on how we can create a gate level netlist from the RTL code and rechnology library. You will also get an idea about the Static Timing Analysis and how that is applied on the RTL to get required results. For this process we have used Design Compiler which is offering from Synopsys. You can use any other software to do synthesis. Also as a technology library we have used SkyWater130nm library.

Table of Contents

• Introduction-to-Logic-Synthesis
• Introduction-to-DC-Tool
• Small-overview-of-TCL
• Basics-of-Static-Timing-Analysis
• Overview-of-SkyWater130nm-library
• Synopsys-Design-Constraints-(SDC)

Introduction-to-Logic-Synthesis

The ASIC design flow starts with the design specification and after that RTL codeing. The RTL code afterwards need to translated into terms of logic cells to fabricate on the silicon. The synthesis is a step where we take RTL code (Verilog, VHDL, etc.), technolnogy library and try to convert the logics written in RTL format to standerd cells format. The .lib file is the source of the technology library, it can be from any of the foundery. Here for this excersize we have used SKYWATER 130nm library.

Now the question is what is the need of this logic synthesis step. We can be happy with the high level RTL code. We can discuss this with a small example. let us take a small verilog code : module model_code (input a, input b, output z) assign z= (a&b) | (b&c) | (c&a); endmodule This can be implemented in multiple ways. Here we have added 3:

implementation 1

implementation 2

implementation 3

And now you maybe confused which one we need because each circuit is logically correct. If I provide you with a tavle with the value of different standerd cells. The table will have delay values and area value like this :

STD CELLS DETAILS

Name	Area (um^2)	Delay(ns)
2 i/p AND	0.1	2
3 i/p OR	0.3	2
2 i/p OR	0.1	1
2 i/p NAND	0.1	1
2 i/p NAND	0.15	1.5

Now if you calculate the figures of delay and area for each implementation you will find out that implementation 3 is good choice in terms of area and timing. But while implementation you will see that always faster cells are not chosen because it depends on the timing paths and criticality. For a path in you design you wante a fast and gate but also in some cases you will see if you provide slower gates it meets the requirement but if you still use a faster gate it will increase in area.

Introduction-to-DC-Tool

Now that we have an idea on the need of logic synthesis we need to discuss the tool that we are using. Why we use tool because logic optimization is a big task to do manually. Here we have used Synopsys Design Compiler. Another reaaon to use this is for mainly the SDC or Synopsys Design Constraints. This file is fed to DC compiler with RTL and .lib file. SDC guides the synthesis tool to extract exadct logic gate optimization and create netlist. The library file as feed to the tool in a .dc format. The netlist this tool churns out is with ectention .ddc.

To open a DC shell ypu have to type in terminal csh and the n dc_shell. The the shell will fire up and it will look something like this :

The DC synthesis flow starts with the technlogy library(.dc/.lib) files as input. DC reads the standerd cell data from library file and try to place suitable cells on the circuit. Thrn there is a command read_verilog . Also dc reads the sdc file. with link command dc links the design with library. Then it starts synthesizing the command is compile_ultra. After compilation is done DC analyses the QoR, generate reports and write out the netlist.

In the read design step DC can read verilog and also 3rd party library files. In DC to provide the library there are 2 variables we have to set. One is target_library and link_library. When the DC fired up in the terminal DC try to get the values of the target_library and link_library values froma file called .synopsys_dc.setup . We can create a file with a same name and set the valriables with the wanted library. In this way we do not have to set these variables each time.

Small-overview-of-TCL

TCL stands for Tool Command Language. The SDC is written in this format. There are also some dc specific commands are mixed. Here we will see some of the tcl instructions. TCL is a bery strongly typed language. Unlike verilog the white space is an issue. We need to be careful about white spaces we provide. \

• set a 5 : This is a way we can set a variable with a value. In this case 'a' is being set to value 5.
• set a [expr $a + $b] : This means the value of 'a' and 'b' are added and stored in variable 'a'.
• $a : Like C pointers is you want to get the value you need to have '$' in front of a variable.
• echo a : echo is a print function here like c pointer it wont print the value it has.
• echo $a : This prints the value 'a' has.
• if {condition} { : Branching statement format. statements; } else { statements; }
• for {looping_var} {condition} {loopin_var increment} { : echo "For Loop format"; statements; }
• foreach varlist { : General TCL statement also used in DC; statements; }
• foreach_in_collection cell_name [collection] { statements; } : Exclusive to DC commands.

example :

Basics-of-Static-Timing-Analysis

Static timing analysis is mainly we see in this step. Here we will discuss what STA basics and what are the things we need to consider. We will take up and example and through that we will try go through the ideas.

In almost all cases a digital circuit can be modelled

Overview-of-SkyWater130nm-library

• Unateness

Synopsys-Design-Constraints-(SDC)

Advance-Constraints

• Circuit-loading

• get_ports * :

• foreach_in_collection

  

  • get_cells

  

  read_ddc design vision

  

  dfrtp - t means true output p for positive edge

  

  

  

  clock

  

  

  

  

  REG2REG contraints

I/O-Delay-modelling

report_port -verbose report-timing -from IN_A

report-timing -to OUT_Y

• lab14_circuit

modified.tcl set_max_delay 0.1 -from [all_inputs] -to [gate_ports OUT_Z]

• after running compile_ultra

• Constraining with vclk set_input_delay -max 5 [get_ports IN_C] -clock [get_clocks MYVCLK] set_input_delay -max 5 [get_ports IN_D] -clock [get_clocks MYVCLK] set_output_delay -max 5 [get_ports OUT_Z] -clock [get_clocks MYVCLK] still violated. now compile_ultra.

slack met report_port -verbose

Combinational Optimization

Resource sharing Multi Check

Setting Max delay from all_input to all_output area RUN1 - without any constraints setting delay from all inputs to all outputr 2.5ns timing met area circuit restricting select path: time violation compile ultra area increase timing slack circuit :

implementation after area contraints to 800 report_area timing report

Sequencial-Optimization

dff_const1 dff_const2 without optimization dff_const4 dff_const5

Boundary-Optimization

DC loads without boundary without boundaer optimization

Register-Retiming

before compile_ultrs -retime

after compiling weith -retime input timing after contraining and retime ![image](https://user-images.githubusercontent.com/56382025/134797384-4ab21443-6fc7-44a1-87d7-a2781570dfd4.png report_timing -from [all_inputs] output slack violated by small margin

Isolating-output-ports

without isolate

After isolating

Multi-cycle-path

without any mcp constrains adding mcp delay -min violated after applying mcp hold

Report_timing

report_timinng -rise_from IN_A -sig 4 -trans -cap -nets > t2.rpt report_timing -rise_from IN_A -sig 4 -trans -cap -nets -to REGA_reg/D > t3.rpt

report_timing -delay_typr min IN_A

report_timing -thorough U15/Y

report_timing -through U15/Y -delay_type min

• check_design
• check_timing
• sourcing the lab9_cons_modified.tcl
• check_timing

High-fan-Net

reading enable_129_mux set_max_delay 3.0 -from [all_inputs] -to [all_outputs] set_max_capacitance 0.025 [current_design] report_constraints -all_violators

Transition problem transition cost report_constraints -all_violators set_max_transition 0.150 [current_design] compile_ultra report_constraints -all_violators diffrnt buffer previously if we do not set the capacitance and transition the the default library values will be considered which is vvwey large.