- Introduction
- Introduction to Logic Synthesis
- Basics to STA
- Advanced Constraints
- 3.1. Clock Tree Modelling - Uncertainty
- 3.2. Loading Design get_cells, get_ports, get_nets
- 3.3. Loading Design get_pins, get_clocks, querying_clocks
- 3.4 Creating Clock Waveforms
- 3.5 Clock Network Modelling - Uncertainty, report_timing
- 3.6 IO Delays
- 3.7 SDC generated_clk
- 3.8 SDC vclk, max_latency, rise_fall IO Delays
- Optimizations
- Quality Checks
Design Compiler is an Advanced Synthesis Tool used by leading semiconductor companies across world. Design Compiler RTL synthesis solution enables users to meet today's design challenges with concurrent optimization of timing, area, power and test. Design Compiler includes innovative topographical technology that enables a predictable flow resulting in faster time to results.
Synthesis in VLSI is the process of converting your code (program) into a circuit. In terms of logic gates, synthesis is the process of translating an abstract design into a properly implemented chip. Synthesis of logic circuits plays a crucial role in optimizing the logic and achieving the targeted performance, area and power goals of an IC.
This workshop includes the following concepts:
- Design fundamentals.
- Setting up DC for synthesis.
- Understanding and Analyzing the STA reports.
- Understanding and writing the Synopsys Design Constraints [SDC].
- Analyzing the quality of netlist synthesized.
The Tools used are:
- Icarus Verilog : For Verilog Compilation, Simulation.
- GTKWave : For viewing the Simulation output.
- Synopsys Design Compiler : For Logic Synthesis
- SAED_PDK 28_32nm Technology Node
Refer : Link for more details
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Design Compiler RTL synthesis solution enables users to meet today's design challenges with concurrent optimization of timing, area, power and test. Design Compiler includes innovative topographical technology that enables a predictable flow resulting in faster time to results. Topographical technology provides timing and area prediction within 10% of the results seen post-layout enabling designers to reduce costly iterations between synthesis and physical implementation. Design Compiler also includes a scalable infrastructure that delivers 2X faster runtime on quad-core platforms.
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Design Compiler is the core of Synopsys' comprehensive RTL synthesis solution, including Power Compiler, DesignWare, PrimeTime and DFTMAX. Design Compiler NXT is also available and includes includes best-in-class quality-of-results, congestion prediction and alleviation capabilities, physical viewer, and floorplan exploration. Additionally Design Compiler NXT produces physical guidance to IC Compiler, place-and-route solution for tighter correlation to layout and faster placement runtime.
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The industry's most comprehensive synthesis solution:
- Benefits:
- Concurrent optimization of timing, area, power and test.
- Results correlate within 10% of physical implementation.
- Removes timing bottlenecks by creating fast critical paths.
- Gate-to-gate optimization for smaller area on new or legacy designs while maintaining timing Quality of Results (QoR).
- Cross-probing between RTL, schematic, and timing reports for fast debug.
- Offers more flexibility for users to control optimization on specific areas of designs.
- Enables higher efficiency with integrated static timing analysis, test synthesis and power synthesis.
- Support for multi voltage and multi supply.
- 2X faster runtime on quad-core compute servers.
//Git Clone sky130RTLDesignAndSynthesisWorkshop.
$ git clone https://github.com/kunalg123/sky130RTLDesignAndSynthesisWorkshop.git
sky130RTLDesignAndSynthesisWorkshop Directory has: My_Lib - which contains all the necessary library files; where lib has the standard cell libraries to be used in synthesis and verilog_model with all standard cell verilog models for the standard cells present in the lib. Ther verilog_files folder contains all the experiments for lab sessions including both verilog code and test bench codes.
read_verilog <file_name>
link
compile_ultra (or) compile
report_power
report_timing
report_area
read_verilog command:
Invoking DC Synthesis:
gedit:
set_target and set_library commands:
Design Vision Invoking:
read_ddc command:
Schematic View:
.lib file is a collection of logical modules which includes all basic logic gates. It may also contain different flavors of the same gate (2 input AND, 3 input AND – slow, medium and fast version).
A cell delay in the digital logic circuit depends on the load of the circuit which here is Capacitance.
Faster the charging / discharging of the capacitance --> Lesser is the Cell Delay
Inorder to charge/discharge the capacitance faster, we use wider transistors that can source more current. This will help us reduce the cell delay but at the same time, wider transistors consumer more power and area. Similarly, using narrower transistors help in reduced area and power but the circuit will have a higher cell delay. Hence, we have to compromise on area and power if we are to design a circuit with low cell delay.
A Constraint is a guidance file given to a synthesizer inorder to enable an optimum implementation of the logic circuit by selecting the appropriate flavour of cells (fast or slow).
Link commands:*
Setting the path to default:
Static timing analysis (STA) is a method of validating the timing performance of a design by checking all possible paths for timing violations. STA breaks a design down into timing paths, calculates the signal propagation delay along each path, and checks for violations of timing constraints inside the design and at the input/output interface.
Clock A digital clock is a repeating digital waveform used to step a digital circuit through a sequence of states. A clock signal oscillates between a high and a low state and is used like a metronome to coordinate actions of digital circuits. A clock signal is produced by a clock generator. Digital circuits rely on clock signals to know when and how to execute the functions that are programmed. If the clock in a design is like the heart of an animal, then clock signals are the heartbeats that keep the system in motion. In serial communication of digital data, clock recovery is the process of extracting timing information from a serial data stream to allow the receiving circuit to decode the transmitted symbols. This is one method of performing a process commonly known as clock and data recovery.
Clock uncertainty is the difference between the arrivals of clocks at registers in one clock domain or between domains. it can be classified as static and dynamic clock uncertainties. Pre-layout and Post-layout Uncertainty. Pre CTS uncertainty is clock skew, clock Jitter and margin. After CTS skew is calculated from the actual propagated value of the clock.
Static clock uncertainty: it does not vary or varies very slowly with time. Process variation induced clock uncertainty. An example of this is clock skew.
Timing Uncertainty of clock period is set by the command set_clock_uncertainty at the synthesis stage to reserve some part of the clock period for uncertain factors (like skew, jitter, OCV, CROSS TALK, MARGIN or any other pessimism) which will occur in PNR stage. The uncertainty can be used to model various factors that can reduce the clock period. It can define for both setup and hold.
Skew: This phenomenon in synchronous circuits. The Difference in arrival of clock at two consecutive pins of a sequential element.
max insertion delay: delay of the clock signal takes to propagate to the farthest leaf cell in the design.
min insertion delay: delay of the clock signal takes to propagate to the nearest leaf cell in the design.
Latency: The delay difference from the clock generation point to the clock endpoints.
Source latency: Source latency is also called insertion delay. The delay from the clock source to the clock definition points. Source latency could represent either on-chip or off-chip latency.
Network latency: The delay from the clock definition points (create_clock) to the flip-flop clock pins.
Jitter: Jitter is the short term variations of a signal with respect to its ideal position in time. It is the variation of the clock period from edge to edge.it can vary +/- jitter value. From cycle to cycle the period and duty cycle can change slightly due to the clock generation circuitry. This can be modeled by adding uncertainty regions around the rising and falling edge of the clock waveform.
Sources of jitter:
Internal circuitry of the PLL. Thermal noise in crystal oscillators. Transmitters and receivers of resonating devices.
get_nets
get_cells
get_ports
get_pins
list_attributes
25% Duty cycle Clock
The process includes:
Commands:
$ report_timing -to REGC_reg/D -delay min
$ report_timing -to REGC_reg/D -delay max
Commands:
$ set_input_delay -max 5 -clock [get_clocks myclk] [get_ports IN_A]
$set_input_delay -max 5 -clock [get_clocks myclk] [get_ports IN_B]
$report_port -verbose
$ set_input_delay -min 1 -clock [get_clocks myclk] [get_ports IN_A]
$set_input_delay -min 1 -clock [get_clocks myclk] [get_ports IN_B]
$report_timing -from IN_A -trans -nosplit
$ set_input_delay -max 5 -clock [get_clocks myclk] [get_ports OUT_Y]
$set_input_delay -min 1 -clock [get_clocks myclk] [get_ports OUT_Y]
$report_timing -from OUT_Y -trans -nosplit
$ set_load -max 0.4 [get_ports OUT_Y]
$report_timing -to OUT_Y -cap -trans -nosplit
$ set_load -min 0.1 [get_ports OUT_Y]
$report_timing -to OUT_Y -cap -trans -nosplit -delay min
Commands:
$ create_generated_clock -source reference_pin [-divide_by divide_factor] [-multiply_by multiply_factor] [-invert] source
Creates a generated clock in the current design at a declared source by defining its frequency with respect to the frequency at the reference pin. The static timing analysis tool uses this information to compute and propagate its waveform across the clock network to the clock pins of all sequential elements driven by this source.
The generated clock information is also used to compute the slacks in the specified clock domain that drive optimization tools such as place-and-route.
$ create_generated_clock -name MYGEN_CLK -master myclk -source [get_ports clk] -div 1 [get_ports out_clk]
$report_clocks *
Virtual clock - purpose and timing
A virtual clock is used as a reference to constrain the interface pins by relating the arrivals at input/output ports with respect to it with the help of input and output delays.
$ create_clock –name VCLK –period 10
Set driving cells
It specifies the drive characteristics of input or inout ports that are driven by the cells in the technology library. These commands associate a library pin with input ports so that delay calculation can be accurately modelled.
VCLK
$ create_clock -name MYCLK -per 10
The Combinational optimization phase transforms the logic-level description of the combinational logic to a gate-level netlist.
Combinational optimization includes:
- Technology-Independent Optimization: This optimization operates at the logic level. Design Compiler represents the gates as a set of Boolean logic equations.
- Mapping: During this process, Design Compiler selects components from the logic library to implement the logic structure.
- Technology-Specific Optimization: This optimization operates at the gate level.
Sequential optimization includes the initial optimization phase, which maps sequential cells to cells in the library, and the final optimization phase, where Design Compiler optimizes timing-critical sequential cells (cells on the critical path):
- Initial Sequential Optimization
- Final Sequential Optimization
Boundary optimization results fastest critical paths and smallest design.
Basically four optimizations collectively called as Boundary optimization in synthesis (with respect to DC):
a) Inversion pushing across hierarchy. b) propagation of equal and opposite information c) propagation of unconnected /undriven ports. d) propagation of constants..
$ set_boundary_optimization u_im false
Register retiming is a circuit optimization technique that moves registers forward or backward across combinational elements in a circuit. The aim of this procedure is to shorten the clock cycle or reduce circuit area. There are two basic types of register retiming: Forward retiming and backward retiming.
A Multi-Cycle Path (MCP) is a flop-to-flop path, where the combinational logic delay in between the flops is permissible to take more than one clock cycle. Sometimes timing paths with large delays are designed such that they are permitted multiple cycles to propagate from source to destination.
$set_multicycle_path -setup 2 -to prod_reg[*]/D -from [all_inputs]
$set_multicycle_path -hold 1 -to prod_reg[*]/D -from [all_inputs]
To start the Physical design these are the files we get input from Synthesis:
- Netlist
- SDC
After receiving database from synthesis team and prior to place and route you can perform some sanity checks. To validate the quality of constraints read in the netlist and the sdc file in the primetime and perform check_timing and generate report which will giving inputs like the quality of database like:
how many of the flip flops are getting clocks, how many flops are constrained, how many ports are having constrained or whether there is any violation like that which will surely give some idea about the quality of the delivered database.
In order to understand the quality of the database interms of timing , generate timing reports and understand the quality of timing how good or how bad is the database and how much you can optimize at the backend or at the placement and routing stages or what paths you cannot meet timing even during placement stages.
After analysing bit on the timing reports you can get some idea of what all areas you need to close pack during placement so that you can create regions.
Generate report_area and report_references -hier report in the designcompiler or synthesis stage to better understand the design hierarchy.
The Report Timing command allows you to specify options for reporting the timing on any path or clock domain in the design.
In a hold timing report, the tool is checking whether the data is held long enough after the clock arrival at the clock port of the flop. i.e. if the data path is faster, the data at the flop edge can change earlier than the stipulated hold time.
Timing path is defined as the path between start point and end point where start point and end point is defined as follows: Start Point: All input ports or clock pins of a sequential element are considered as valid start point. End Point: All output port or D pin of sequential element is considered as End point.
The main goal of static timing analysis is to verify that despite these possible variations, all signals will arrive neither too early nor too late, and hence proper circuit operation can be assured. Since STA is capable of verifying every path, it can detect other problems like glitches, slow paths and clock skew.
report_timing:
check_timing: Checks the assertions and structure of the design for potential timing violations.This command is used to identify possible problems before generating timing or constraint reports. This command also prints which checks it performs. If a check reveals a violation, the command also prints a message about the violation. By default, the message contains a summary of the violation. To get more information about violations, use the -verbose option.
Check_design: check_design checks the current design for consistency. The check_design command checks the internal representation of the current design for consistency, and issues error and warning messages as appropriate.
Set_max_capacitance: Specifies a maximum capacitance on pins, ports or design. If maximum capacitance is set on a pin or port, the net connected to that pin or port is expected to have a total capacitance less than the specified capacitance_value. If specified on a design, the default maximum capacitance for that design is set. Library cell pins also can have max_capacitance value specified.
HFN: High Fanout Net Synthesis (HFNS) is the process of buffering the High Fanout Nets to balance the load.
en_128:
mux_generate_128_1:
- Kunal Ghosh, Co-founder, VSD Corp. Pvt. Ltd.
- A Devipriya, B.E (Electronics and Communication Engineering), Bangalore - adevipriya1900@gmail.com