Physical Verification (PV) Using Synopsys 40nm

Table of Contents

1. Overview
   • VLSI Design Flow chart
   • KeyTerms
   • Before steps to Physical Verification
     • PHYSICAL DESIGN STEPS
2. Introduction to Physical Verification
   • DRC (Design Rule Check)
   • LVS (Layout vs Schematic)
   • ARC (Antenna Rule Checking)
   • ERC (Electrical Rule Checking)
3. Verification Tools
   • Overview
     • Tools to Invoke
   • Understanding of Synopsys EDA Tools for Verification
     • IC Validator (ICV)
       • ICV DRC
       • ICV LVS
4. Designing of an Inverter
   • CMOS Inverter Working
     • Inverter Schematic Diagram
   • Library Characterization
     • How Does Library Characterization Work?
   • Library and Cell View creation
   • Schematic Creation
   • Symbol Creation
5. Analysis of an Inverter
   • Inverter Static Characteristics or VTC
   • Inverter Dynamic Characteristics
   • Creating TestBench
   • Simulation on PrimeWave
     • DC Analysis
   • Netlist and log Display
     • Synopsys Design Constraints
     • Netlist run
     • Log
6. Layout Creation
   • Schematic Driven Layout (SDL)
     • Execution
   • Routing
     • Execution
7. Physical Verification-SignOff Checks
   • DRC
     • Execution
   • LVS
     • LVS Flow
       • Commonly faced LVS issues
       • IR Drop Analysis
     • Execution
   • XOR
     • Execution
8. Acknowledgements
9. Author
10. References

Overview

VLSI Design Flow chart

Very Large Scale Integration(VLSI) is the process of making Integrated Circuits (ICs) by combining a number of components like resistors, transistors, and capacitors on a single chip.

VLSI Design is an iterative cycle. Designing a VLSI Chip includes a few problems such as functional design, logic design, circuit design, and physical design. The design is verified for accuracy by the process of simulation.

If any design errors are found at any stage of verification, at least one of the previous design steps must be repeated to correct the error during the process of designing.

1. System specification: The objective of the desired final product is written in this step. During system specification, the designated cost of the system, its performance, architecture, and how the system will communicate with the external world are to be determined. During this step, the design specification should be provided by the users or clients.

2. Architectural design: The basic architecture of the desired design must meet the system specifications of the desired design. The architecture of the desired design is decided and the layout for the same is designed by design engineers. Architectural design includes the integration of analog and mixed-signal blocks, memory management, internal and external communication, power requirements, and choice of process technology and layer stacks.

3. Functional design or Behavioural design: It consists of refining the design specification of the desired design in order to design the functional behavior of the desired system. The main objective of this is to generate design a high-performance architectural design within the cost requirements posed by the specifications.

4. Logic Design: In this step, the structure of the desired design is added to the behavioral representation of the desired design. The main specifications to be considered for logic design are logic minimization, performance enhancement, and testability. Logic design must also consider the problems associated with test vector generation, error detection, and error correction. Many logic synthesis tools have been developed for the automation of the process of logic design.

5. Circuit Design: In this step, the logic blocks of the desired design are replaced by the electronic circuits, which are consists of electronic devices such as resistors, capacitors, and transistors. Circuit simulation of the desired design is done at this stage, in order to verify the timing behavior of the desired system. Kirchhoff’s laws are used to know the behavior of the electronic circuit in terms of node voltages and branch circuits. The result of integrodifferential equations is then solved in discrete- time. SPICE is a well-known program for circuit simulation.

6. Physical Design: In this step, the actual layout of the desired system is done, where all the components will be placed in the circuit and all these components are interconnected. The actual layout of the desired system can affect the area, correctness, and performance of the final desired product. The correctness of the chip is also controlled by the physical design. A circuit design that passes the test of a circuit simulator may be faulty after it has been packaged. This is because of geometric design rule errors. These design rules must be followed to ensure the correctness of the chip fabrication. Errors such as short circuits, open circuits, open channels, etc may result if the design rules are not respected.

7. Fabrication: After the actual layout and verification of the desired design, the design is sent for manufacturing. The handoff of the desired design to the manufacturing process is called tapeout. Generation of the data for manufacturing is referred to as streaming out. The desired design is onto the different layers of the design using the photolithographic process. ICs are manufactured on round silicon wafers with a diameter from 200mm to 300mm, these ICs are then tested and are marked as either functional or defective ICs.

8. Packaging and Testing: After fabrication of desired design, functional chips are then packed. Packaging is configured early in the desired design process and the application along with the cost and form factor requirements. Packaged types may include Dual In-Line Packaged (DIPs), Pin Grid Array (PGAs), and Ball Grid Arrays (BGAs). After a die is positioned in the package cavity, its pins are connected to the pins of the package, e.g., with wire bonding or solider bumps (flip-chip). The package of the desired design is then sealed and then sent to the end-users or clients.

KeyTerms

• Custom : Is a method of creating integrated circuits that specifies the architecture (Like, Analog) of each individual transistors as well as inter connections (via, contacts).
• Custom Jobs : Custom Compiler Design Checking and Physical Verification
• Design Specifications: Customer requirements  PDK file, Input elements, Technology file
• Schematic Capture: Circuit creation
• Symbol Creation: Creating the schematic into symbol
• Simulation: Pre-Layout Simulation  PrimeWave
• Layout: SDL, LE(Layout Editor)
• Parasitic extraction: Extracting the binary coefficient values of resistor and capacitor.

Before steps to Physical Verification

The main steps in the physical design flow are:

• Design Netlist (after Synthesis)
• Floorplanning
• Partitioning
• Placement
• Clock-Tree Synthesis (CTS)
• Routing
• Physical Verification
• GDS II Generation

The physical design flow uses the technology libraries that are provided by the fabrication houses. Technologies are commonly classified on the basis of minimal feature size. The basic sizes available are 2µm, 1 µm, 0.5 µm, 90nm, 45nm, 18nm, 14nm, etc. They may also be classified according to the manufacturing process like: n-well process, twin well process, SOI process etc.

The steps of design flow are explained below:

DESIGN NETLIST: Physical Design is based on a netlist which is the end result of Synthesis process. The netlist contains information on the cells used, their interconnections, area, and other details. Synthesis tools that are used are:

Cadence RTL Compiler/Build Gates Synopsys Design Compiler

During the synthesis process, all the constraints are applied to ensure the design meets the functionality and speed. Once the timing and functionality is verified, it is sent for physical design flow.

PHYSICAL DESIGN STEPS

1. FLOOR-PLANNING: The first step in physical design is floor planning. In this process, the structures are identified which should be placed together meeting the performance and timing requirements. The desire to have everything close to everything else is followed. But based on the area and hierarchy, a suitable floor plan is decided. Floor planning is defined as taking account of macros used in the design, memory, other IP cores and their placement needs, the routing possibilities and also the area of the entire design. Area and Speed are two factors which can be trade off against one another. Optimizing the design for minimum area allows the design to use fewer resource and thus increasing the speed of the system.

As a general rule, data-path benefit most from floor planning, and other logics like state machines, or some random logic are placed to the left section of the place and route software.

2. PARTITIONING: It is a process of dividing the chips into small blocks. This is done mainly to separate functional block and also to make placement and route easier. Partitioning can be done in the designing phase as the design engineer usually divides the whole system to sub-blocks and then proceeds to design each module. These sub modules/blocks are later connected in TOP LEVEL module.

3. PLACEMENT: Before the placement, all Wire Load Models(WLM) are removed. Placement uses RC values from Virtual Route(VR) to calculate timing. Placement can be done in four phases:

I. Pre-placement optimization: In this process optimization happens before netlist is placed. In this process high-fan out nets are collapsed downsizing the cells.

II. In placement optimization: In this process logic is re-optimized according to the VR. Cell bypassing, cell moving, gate duplication, buffer insertion, etc. can be performed in this step.

III. Post Placement optimization: Netlist is optimized with ideal clocks before CTS. It can fix setup, hold violations. Optimization is done based on global routing.

IV. Post placement optimization after CTS optimization: Optimization is performed after the CTS optimization is done using propagated clock. It tries to preserve the clock skew.

4. CLOCK TREE SYNTHESIS (CTS):

I. Ideal clock before CTS: The goal of CTS is to minimize the skew and insertion delay. Clock is not propagated before CTS. If clock is divided the separate skew analysis is done. Global skew achieves zero skew between two synchronous pins without considering logic relationship and local skew achieves zero skew between two synchronous pins while considering logic relationship. If clock is skewed intenetionally to improve the setup slack then it is known as useful skew.

II. Clock After CTS: In clock tree optimization cloak can be shielded to remove noise. But shielding increases area by 12% to 15%. Optimization is achieved by gate sizing, buffer sizing, level synthesis and HFN synthesis. Hold slack is improved in optimization after CTS. As a result of CTS a lot of buffers are added.

5. ROUTING: There are two types of routing in physical design process:

I. Global Routing: In this type of routing a loose route is generated for each net with estimated values. Rough estimation of values can be done by calculating the delays for fanout of wire. Global Routing is further divided into Line Routing and Maze Routing.

II. Detailed Routing: In detailed routing the actual geometry layout of each net is calculated i.e actual delays of wire is calculated. The actual delays can be obtained by several optimizations like Timing optimization, CTS, etc.

6. PHYSICAL VERIFICATION: Physical verification checks the correctness of generated layout design. This includes:

I. DRC (Design Rule Check) II. LVS(Layout vs. Schematic) III. ARC (Antenna Rule Checking) IV. ERC (Electrical Rule Checking)

7. GDS II: Graphic Database System: GDS II is a database file format which is the industry standard for data exchange of IC layout artwork. It is a binary file representing planar geometric shapes, text labels and other information about the layout in hierarchical form.

Introduction to Physical Verification

After routing, your PnR tool should give you zero DRC/LVS violations. However, the PnR tool deals with abstracts like FRAM or LEF views. We use dedicated physical verification tools for signoff LVS and DRC checks. Some of these are Hercules from Synopsys, Assura from Cadence and Calibre from MentorGraphics.

The major checks are, as mentioned above in previous section:

• DRC
• LVS
• Antenna
• ERC

DRC (Design Rule Check)

DRC checks determine if the layout satisfies a set of rules required for manufacturing. The most common of these are spacing rules between metals, minimum width rules, via rules etc.There will also be specific rules pertaining to your technology. An input to the design rule tool is a ‘design rule file’ (called a runset by Synopsys’ hercules).

The design rules ensure sufficient margins to correctly define the geometries without any connectivity issues due to proximity in the semiconductor manufacturing processes, so as to ensure that most of the parts work correctly. The minumum width rules exists for all mask layers, and spacing between the same layers are also specified. Spacing rules may change depending on the width of one or both of the layers as well. There can also be rules between two different layers, and specific via density rules etc.

If the design rules are violated, the chip may not be functional. DRC checking software, like Assura, Hercules or Calibre usually takes the layout in any of the supported formats, like GDSII.

LVS (Layout vs Schematic)

LVS is another major check in the physical verification stage. Here you are verifying that the layout you have created is functionally the same as the schematic/netlist of the design-that you have correctly transferred into geometries your intent while creating the design. So all the connections should be proper and there shouldn’t any missing connections etc.

The LVS tool creates a layout netlist, by extracting the geometries. This layout netlist is compared with the schematic netlist. The tool may require some steps to create either of these netlists(e.g. nettran run in synopsys)

If the two netlists match, we get an LVS clean result. Else the tool reports the mismatch and the component and location of the mismatch. Along with formal verification, which verifies if your pre-layout netlist matches the post-layout netlist,LVS verifies the correctness of the layout w.r.t intended functionality.

Some of the LVS errors are:

1. Shorts – Wires that should not be connected are overlapping.
2. Opens – Connections are not complete for certain nets.
3. Parameter mismatch – LVS also checks for parameter mismatches. e.g. It may match a resistor in both layout and schematic, but the resistor values may be different. This will be reported as a parameter mismatch.
4. Unbound pins – If the pins don’t have a geometry, but all the connection to the net are made, and unbound pin is reported.

ARC (Antenna Rule Checking)

Process antenna effect or “plasma induced gate oxide damage” is a manufacturing effect. i.e. this is a type of failure that can occur solely at the manufacturing stage. This is a gate damage that can occur due to charge accumulation on metals and discharge to a gate through gate oxide.

In the manufacturing process, metals are built layer by layer. i.e. metal1 is deposited first, then all unwanted portions are etched away, with plasma etching. The metal geometries when they are exposed to plasma can collect charge from it. Once metal1 is completed, via1 is built, then metal2 and so on. So with each passing stage, the metal geometries can build up static electricity. The larger the metal area that is exposed to the plasma, the more charge they can collect. If the charge collected is large enough to cause current to flow to the gate, this can cause damage to the gate oxide. This happens because since the layers are built one-by-one, a source/drain implant may not be available for discharge as in fig.b.

Antenna rules are normally expressed as an allowable ratio of metal area to gate area. Each foundry sets a maximum allowable antenna ratio for its processes. If the metal area–which is cumulative, i.e. the sum of the ratios of all lower layer interconnects in addition to the layer in check–is greater than the allowable area, the physical verification tool flags an error.For example, let’s say maximum allowable antenna ratio for metal1 is 400. If the gate area is 1 sq.u and if the metal area connecting to the gate is 500 sq.u, there will be a process antenna violation.

ERC (Electrical Rule Checking)

ERC (Electrical rule check) involves checking a design for all electrical connections that are considered dangerous.

1. Floating gate error – If any gate is unconnected, this could lead to leakage issues.
2. VDD/VSS errors – The well geometries need to be connected to power/Ground and if the PG connection is not complete or if the pins are not defined, the whole layout can report errors like “NWELL not connected to VDD.

Verification Tools

Overview

1. Custom Compiler:

• The Synopsys Custom Compiler design environment is a modern solution for full-custom analog, custom digital, and mixed-signal IC design. Custom Compiler provides design entry, simulation management and analysis, and custom layout editing features.
• The Custom Compiler design environment includes features for mixed-signal design entry, design debug, simulation management, analysis, and reporting.
• For layout, Custom Compiler provides fast and user-friendly polygon editing features and boosts productivity with its pioneering visually-assisted automation flow. Visually assisted automation is an innovative approach that delivers 2-10X better layout productivity—especially for difficult FinFET-based designs.
• Custom Compiler includes built-in verification features to catch physical and electrical errors during layout. These include design rule checking, electromigration checking, and resistance and capacitance extraction.
• The Custom Compiler design environment makes it easy to communicate design intent and achieve analog design closure, with support for templates and early parasitic simulation.
• For more information you may check at https://www.synopsys.com/implementation-and-signoff/custom-design-platform/custom-compiler.html

2. IC Validator:

• IC Validator physical verification is a comprehensive and high-performance signoff solution that improves productivity for customers at all process nodes, from mature to advanced. IC Validator offers the industry’s best distributed processing scalability to over 4,000 CPU cores.
• The tool’s performance and scalability enabled some of the industry’s largest reticle limit chips with billions of transistors, same-day design rule checking (DRC), layout versus schematic (LVS), and fill turnaround time.
• IC Validator is seamlessly integrated with the Synopsys Fusion Compiler RTL-to-GDSII solution and IC Compiler II place and route system in the Fusion Design Platform.
• This integrated fusion technology accelerates design closure for manufacturing by enabling independent signoff-quality analysis and automatic repair within the implementation environment.
• For more information you may check at https://www.synopsys.com/implementation-and-signoff/physical-verification.html

3. PrimeWave:

• PrimeWave Design Environment is a comprehensive and flexible environment for simulation setup and analysis of analog, RF, mixed-signal design, custom-digital and memory designs within the Synopsys Custom Design Platform.
• It delivers a seamless simulation experience around all the engines of Synopsys PrimeSim solution, with comprehensive analysis, improved productivity, and ease of use.
• PrimeWave Design Environment also offers powerful Tcl-based scripting capability enabling easy regressions across thousands of corners.
• For more information you may check at https://www.synopsys.com/implementation-and-signoff/ams-simulation/primewave.html

Tools to Invoke

The tools that I had invoked for the labs in terminal are listed below:

module load primewave
module load hspice
module load cx
module load primesim
module load icv
module load customcompiler
custom_compiler &

The version that I used for invoking all the tools are: 2022.06-SP1
You may invoke it without mentioning the version, as it will take the latest version available. Else, if you wish to invoke a specific version then you may mention it as follows: module load primewave/2022.06-SP1

Understanding of Synopsys EDA Tools for Verification

• If you are looking for steps to install the Synopsys EDA Tools you may check out from the official Website: Synopsys
• The details are mentioned below for DRC and LVS.

IC Validator (ICV)

• For details visit the Link

ICV DRC

• Firstly from the link: [https://www.synopsys.com/implementation-and-signoff/resources/videos/drc-three.html], Learn how to run Design Rule Checks (DRC) interactively from IC Validator VUE interface.
• IC Validator VUE is a flow based graphical tool that guides you through the entire physical verification flow. Within one interface, you can configure and execute a verification run, easily load the results, review a run summary, and debug the design by highlighting errors within most layout editor tools.
• For technical videos on IC Validator DRC you may check at : https://video.synopsys.com/icvalidator/category/videos/ic-validator-technical-videos:-drc

ICV LVS

• Layout Versus Schematic (LVS) checking compares the extracted netlist from the layout to the original schematic netlist to determine if they match.
• The comparison check is considered clean if all the devices and nets of the schematic match the devices and the nets of the layout.
• Optionally, the device properties can also be compared to determine if they match within a certain tolerance. When properties are compared, all the properties must match as well to achieve a clean comparison.

LVS Flow:

• Two main processes make up the LVS flow. The first process in the flow is extraction, in which the layers within the layout database are analyzed and all the devices and nets are extracted. The second process in the flow is compare, in which the actual comparison of devices and nets occurs.
• The LVS runset contains a series of function calls that control both extraction and netlist comparison.

Common LVS issues: LVS errors can be classified into two main categories:

1. Extraction Errors

• Text short and open
• Device extraction error
• Missing device terminal
• Extra device terminal
• Unused text
• Duplicate structure placement

2. Compare Errors

• Unmatched nets in the layout/schematic

• Unmatched devices in the layout/schematic

• Property errors

• Port swap errors

• Content source Link

• For technical videos you may check at: https://video.synopsys.com/icvalidator/category/videos/ic-validator-technical-videos:-lvs

Designing of an Inverter

CMOS Inverter Working

• The term “CMOS” stands for “complementary-symmetry metal–oxide–semiconductor” which is pronounced as “see mos”. CMOS is a type of MOSFET, where its fabrication process uses complementary & symmetrical P-type & N-type MOSFET pairs for logic functions.
• The main CMOS devices characteristics are consumption of low static power & high noise immunity. The inverter is accepted universally as the basic logic gate while performing a Boolean operation on a single i/p variable.
• A basic inverter circuit is used to accomplish a logic variable by complementing from A to A’. So, a CMOS inverter is a very simple circuit, designed with two opposite-polarity MOSFETs within a complementary way.
• The logic element like an inverter reverses the applied input signal. In digital logic circuits, binary arithmetic & switching or logic function’s mathematical manipulation are best performed through the symbols 0 & 1. If the input logic is zero (0) then the output will be high (1) whereas, if the input logic is one (1), then the output will be low (0).

Inverter Schematic Diagram

• CMOS inverter definition is a device that is used to generate logic functions is known as CMOS inverter and is the essential component in all integrated circuits.
• A CMOS inverter is a FET (field effect transistor), composed of a metal gate that lies on top of oxygen’s insulating layer on top of a semiconductor. These inverters are used in most electronic devices which are accountable for generating data n small circuits.

Library Characterization

• Cell library characterization is a process of analyzing a circuit using static and dynamic methods to generate models suitable for chip implementation flows.
• Knowing the logical function of a cell is not sufficient to build functional electrical circuits. More aspects need to be considered; for example, the speed of a single cell will influence the speed of the full circuit, just as the power used by a single cell can influence the total power.
• Further, the speed as well as the power might be influenced by the output load. Standard-cell characterization aims at collecting this sort of information.
• Library characterization is a process of simulating a standard cell using analog simulators to extract input load, speed, and power data in a way that the downstream tools can process it all.
• This can be done via a specific analog simulator whose output is used to generate the characterization data, or by using a library characterization tool.

How Does Library Characterization Work?

• For digital library characterization, some of the views are usually provided by the design while others must be derived. For instance, the logic function of a NAND gate could be defined as "!(A & B)." In principle, all other views can be derived from this equation using some additional assumptions and constraints, depending on the technology and design goals.
• The netlist of combinatorial cells can be generated algorithmically. Starting from the netlist, a layout will be drawn which can be used to extract parasitic capacitances and resistances within the cell. The resulting netlist of transistors and parasitics can be further used to get an abstract description of the cell’s timing, power, and noise behavior.
• One way to derive timing and power numbers is through simulation of the transistor netlist. However, one simulation is not enough because the cell’s behavior strongly depends on other factors, such as process, voltage, and temperature (PVT), input wave form, and output load.
• A common approach is to look at the best and worst PVT conditions. Effectively, this allows you to predict lower and upper bounds of the cell behavior, which are important to ensure the overall functionality of the design.
• Further, cells must be characterized over a reasonably large range of input edge rates and output load. For example, a cell could be characterized on a two-dimensional grid with variable input edge rate and output load (non-linear delay model). If the grid points are chosen correctly, then the behavior between grid points can be approximated by linear interpolation.
• Cell library characterization typically takes cell design extracted as SPICE circuit and SPICE technology models. The characterization tool analyzes this information to:

1. Acquire the functionality of the cell
2. Generate stimulus to produce the characterization decks
3. Simulate the decks using a circuit simulator
4. Gather the simulation output
5. Write this data into standard models, like Liberty™, Verilog, or IBIS

• For more details: Source Link

Library and Cell View creation

1. Invoke Custom Compiler (CC) from your terminal module load custom_compiler & and your window should look something like this:

2. Go to File --> New --> Library as shown below:

3. A dialog box appears as shown below. Enter the Name and select the Technology Node, as in my case it is reference40nm and then Click OK.

4. After which a New Library gets created with the name that you gave. Then for creating a new cell view, Go to File --> New --> CellView as shown below:

5. CellView dialog box appears. Choose the options as shown below and then Click OK.

6. Schematic Window will open as shown below:

Schematic Creation

1. Click on Instance as shown in the figure or press I on screen

2. In the Library section, select the Technology node that you used to create the Library and select p_4t, n_4t devices from the options available one by one. In the Parameters section, enter the vlues as shown in the fig below.

3. Place them on the window one by one.

4. Select Add Pin as shown in the below figure and place it on the screen.

In the Name section type Vin, VDD, VSS, Vout by selecting the Type to Input, Input, Input, Output one after the other and place them on the schematic editor window.

5. Add wire by the clicing the option shown below:

6. And, join all the circuit elements as shown below:

Symbol Creation

For creating the Inverter symbol follow the steps as shown below:

1. Go to Design --> New CellView --> From CellView

2. Dialog box appears to be as shown below. Click OK.

3. Inverter symbol will be created as shown below:

4. You may delete the other options present in the snapshot above and make it to look like this as shown below:

Analysis of an Inverter

The characteristics of the CMOS inverter are discussed below.

Inverter Static Characteristics or VTC

• The quality of the inverter can be measured frequently by using the VTC or voltage transfer curve, which is plotted between input voltage (Vin) and output voltage (Vo). From the following static characteristics, the parameters of devices like gain, operating logic levels & noise tolerance, and noise can be obtained.

• The VTC or voltage transfer curve looks like an inverted step-function that specifies accurate switching in between ON & OFF however in real devices, a gradual transition region exists. The voltage transfer curve specifies that for less input voltage Vin, the circuit generates high voltage Vout, whereas, for high input, it generates 0 volts.
• The transition region slope is a measure of quality – steep slopes yield exact switching. The tolerance toward noise can be calculated by evaluating the smallest input to the highest output for every region of ON or OFF operation.

Inverter Dynamic Characteristics

• The CMOS inverter dynamic characteristics are shown below. So, some of the following formal definitions of different parameters are discussed below. Here, all the percentage (%) values are the steady-state values.

• Rise Time or tr: Rise time is the time used to increase the signal from 10% to 90%.
• Fall Time or tf: Fall time is the time used to drop the signal from 90% to 10%
• Edge Rate or trf : It is (tr + tf )/2.
• The propagation delay from high to low or tpHL: The time used to drop from VOH – 50%.
• The propagation delay from low to high or tpLH: The time used to increase from 50%- VOL.
• Propagation Delay or tp: It is (tpHL + tpLH)/2.
• Contamination Delay or tcd: It is the smallest time from the 50% input crossing to the 50% output crossing.

Follow the steps below in order to get the DC Analysis of an Inverter.

Creating TestBench

1. Create a new CellView and name it as testbench (inverter_tb) as shown in the below figure:

2. Add Instance of an Inverter that you created earlier in the exercise by either clicking on the Instance shortcut on the left side bar or simply press I by following the steps shown below:

3. Add Vdc (Voltage supply) by selecting the options shown below:

4. Add gnd (Ground) by selecting the options shown below:

5. Connect them in the following way:

Simulation on PrimeWave

1. Select Tools --> PrimeWave

2. Setup --> Model Files --> Include the hspice path from the directory --> Click to add and add the .lib file --> Under Section, Select TT --> Click OK

3. Setup --> Analyses --> Analysis Type: dc --> Source Name: Select the Vdc pin that connects to Vin (In my case, it is V8) --> Give Start, Stop and Step size values as shown below --> In the bottom left corner, Click on Enable --> Click OK

4. Simulation --> Options --> Under Simulation Engine: PrimeSim HSPICE (Rest options, leave default) --> Click OK

5. Outputs --> Add from Design

6. Click on the Input and Output Net (Vin and Vout) as shown below:

7. Your inverter_tb window should now look something like this:

8. Simulation --> Netlist and Run

DC Analysis

• Analyze DC Characteristics of CMOS Gates by studying an Inverter.

• DC Analysis: – DC value of a signal in static conditions

• DC Analysis of CMOS Inverter: – Vin, input voltage – Vout, output voltage – single power supply, VDD – Ground reference – find Vout = f(Vin)

• Voltage Transfer Characteristic (VTC): – plot of Vout as a function of Vin – vary Vin from 0 to VDD (and in reverse!) – find Vout at each value of Vin

9. DC Analysis of an Inverter:

Netlist and log Display

Synopsys Design Constraints

• Timing closure is the big whale for most P&R designers. You get it done, and then you can wash your hands off all those annoying designers and get to work cleaning up and beautifying your layout.
• So I thought of starting my P&R cheat sheet with an introduction to timing closure, and what best to address than the mighty SDC constraints, the bane of all our existence. You get the SDC right, you win half your battle. But it is not so simple.
• SDC you get from the synthesis tool might have very well served its purpose there, but to get it do a pretty good job in layout requires some time spent on understanding and iterating the design.

1. Clock Statements
2. False path Specifications
3. Specifying operating conditions
4. Specifying Ideal Networks – No optimizations required
5. set_input_delay
6. set_max_delay
7. set_driving_cell
8. set_load

• There are countless other commands in SDC format, but these are the most common. Try to simplify your SDC as much as possible, and you can pin point the errors and issues easier.
• For more details visit the Link

Netlist run

• A netlist is a textfile containing the description of components connection. Component id , what is its value or name and the nodes its pins are connected.

• Spice netlist is an input file where user writes them and use it for simulation. Also used at the vlsi design where at the end of design phase the netslist is generated from layout and used for verification.

• Netlist perse is used in the PCB design for layout and routing of tracks.

• Netlist can be defined as the piece of code, which describe a circuit in textual form for interpretation by computer. Any simulation software uses some kind of textual description which is converted to machine understandable language.

• You can view the netlist file by simply going to Simulation --> Netlist --> Display

• Below snapshot shows you the Netlist file:

Log

• To view the log file Simulation --> Display log

• You can explore and try to understand the other files generated as well. Below snapshot shows the hspice.st0 file:

Layout Creation

Basic Design Rules:

Schematic Driven Layout (SDL)

• The schematic-driven layout (SDL) flow in CC helps create an optimized layout that is DRC/LVS-correct in less time—without sacrificing layout area. Both netlist and schematic views are included with the CC layout editor for an intuitive SDL working environment, which includes:

- Schematic view and design browser
- Advanced layout editor, including rule-driven layout, flight-line guidance and short detection
- Realize, place, route, and edit a physical layout that is DRC- and LVS-correct

Execution

1. Tools --> Check SDL Option

2. Physical Target Dialog box appears. Click Ok by checking with the details.

3. SDL --> Generate Layout

4. After the previous step, A dialog box appears wherein you can leave the options default or you may check with the options by trail and error to see which one works good for you and then Click OK --> You will now be able to see what is displayed on the snapshot below. Press Shift+F in order to view the circuit elements.

5. Arrange the pmos, nmos and the pins as shown below or you may arrange it differently to check or experiment.

Routing

• Routing is the process of creating physical connections based on logical connectivity. Signal pins are connected by routing metal interconnects. Routed metal paths must meet timing, clock skew, max trans/cap requirements and also physical DRC requirements.
• In grid based routing system each metal layer has its own tracks and preferred routing direction which are defined in a unified cell in the standard cell library.
• There are four steps of routing operations:

1. Global routing
2. Track assignment
3. Detail routing
4. Search and repair

• Global Route assigns nets to specific metal layers and global routing cells. Global route tries to avoid congested global cells while minimizing detours. Global route also avoids pre-routed P/G, placement blockages and routing blockages.
• Track Assignment (TA) assigns each net to a specific track and actual metal traces are laid down by it. It tries to make long, straight traces to avoid the number of vias. DRC is not followed in TA stage. TA operates on the entire design at once.
• Detail Routing tries to fix all DRC violations after track assignment using a fixed size small area known as “SBox”. Detail route traverses the whole design box by box until entire routing pass is complete.
• Search and Repair fixes remaining DRC violations through multiple iterative loops using progressively larger SBox sizes.

Execution

1. Click on Tools --> Routing from the window

2. Once you enable Routing option, On the Toolbar you will now be able to see the Routing option. Go to Routing --> Auto Route. This option will let you to do the routing automatically. If you wish to do the Routing manually you may try by using the metal layers available.

3. Click on ALL option from the Nets category. Click on tick option in green color and then check the option.

4. Your Layout will look something like this as shown below. If you got it, then that is amazing. Let's now go to DRC.

Physical Verification-SignOff Checks

DRC

• Design Rule Check (DRC) determines whether the layout of a chip satisfies a series of recommended parameters called design rules. Design rules are set of parameters provided by semiconductor manufacturers to the designers, in order to verify the correctness of a mask set.

• It varies based on semiconductor manufacturing process. These rule set describes certain restrictions in geometry and connectivity to ensure that the design has sufficient margin to take care of any variability in manufacturing process.

• Input files required for DRC • GDS • drc rule deck file

• Output of DRC • Reports

• Typical DRC rules are :

1. Interior:

Fig1: Distance of interior facing edge for a single layer. Fig2: Distance of interior facing edge of two layer.

2. Exterior:

Fig3: Distance of exterior facing edge of two layer

3. Enclosure:

Fig4: Distance between inside edge to outside edge.

4. Extension:

Fig4: Distance between inside edge to outside edge.

Execution

1. Go to Verification --> DRC --> Setup and Run and then the Dialog box will appear.

2. DRC Setup box will appear. Keep the options default but if in case any options are not selected, then select them accordingly.

Check for Layer map file from Custom options tab as shown below if it is not selected by default.

3. If no errors then VUE (Visualization User Environment) window will appear saying the layout is DRC clean.

4. In the output directory many files are generated. The snapshot below shows the file from the text editor window which shows the DRC Clean status.

5. Now let's try to generate some errors to see how VUE window displays if any error occurs. I have tried to keep the nmos-pmos spacing to <0.08

6. Now once again try to run DRC, VUE window will generate the errors as shown below:

7. You may check the errors description and try to correct them by looking into the DRC Errors tab in VUE. You can double click on the errors in the error list and check for where the error has occurred.

NOTE: The output generated files are listed below,

- dff.LAYOUT_ERRORS  - Short summary on the error status whether is it CLEAN or errors occurred.
- dff.RESULTS  - ICV Execution (Pathss), Results Summary (Viloations, rules check), Assign Layer Statistics (Utilized layer or unoccupied), Run Configuration (Processing details –CPU, RAM), Performance Statistics (Runtime seconds, memory usage).
- dff.vue - We can configure and execute a verification run. It easily loads the results and reviews a run summary. Debugs the design by highlighting errors.
- icv.log and stdout.drc.log - Log information
- prefs.xml - It contains the details such as cell name, version, library name, path, run dir, etc. 
- run_details - It is a directory that contains all the rules, tech information that is needed to run the DRC.
- run_icv.sh - Contains the path related information.
- stdout.icvVue.log - Contains the color related information of the layout (cells, Blocks, vertical & horizontal routing).

LVS

DRC only verifies that the given layout satisfies the design rules provided by the fabrication unit. It does not ensure the functionality of layout. Because of this, idea of LVS is orginated. This blog focuses on how LVS works and what all are the common issues faced in LVS.

Input files required for LVS

• .v – netlist of the design
• GDS – layout database of the design
• LVS rule deck

Outputs for LVS

• reports

LVS Flow

• .v and GDS should be of same stage :

LVS rule deck is a set of code written in Standard Verification Rule Format (SVRF) or TCL Verification Format (TVF). It guides the tool to extract the devices and the connectivity of IC’s. It contains the layer definition to identify the layers used in layout file and to match it with the location of layer in GDS. It also contains device structure definitions.

• LVS check involves three steps :

  1. Extraction: The tool takes GDSII file containing all the layers and uses polygon based approach to determine the components like transistors, diodes, capacitors and resistors and also connectivity information between devices presented in the layout by their layers of construction. All the device layers, terminals of the devices, size of devices, nets, vias and the locations of pins are defined and given an unique identification.

  2. Reduction: All the defined information is extracted in the form of netlist.

  3. Comparison: The extracted layout netlist is then compared to the netlist of the same stage using the LVS rule deck. In this stage the number of instances, nets and ports are compared. All the mismatches such as shorts and opens, pin mismatch etc.. are reported. The tools also checks topology and size mismatch.

Commonly faced LVS issues

• LVS check includes following comparisons:

  • Number of devices in schematic and its layout • Type of devices in schematic and its layout • Number of nets in schematic and its layout

• Typical errors which can occur during LVS checks are:

  1. Shorts: Shorts are formed, if two or more wires which should not be connected together are connected.
  2. Opens: Opens are formed, if the wires or components which should be connected together are left floating or partially connected.
  3. Component mismatch: Component mismatch can happen, if components of different types are used (e.g, LVT cells instead of HVT cells).
  4. Missing components: Component missing can happen, if an expected component is left out from the layout.
  5. Parameter mismatch: All components has it’s own properties, LVS tool is configured to compare these properties with some tolerance. If this tolerance is not met, then it will give parameter mismatch.

IR Drop Analysis

• IR Drop can be defined as the voltage drop in metal wires constituting power grids before it reaches the vdd pins of the cells. IR drop occurs when there are cells with high current requirement or high switching regions. IR drop causes voltage drop which in-turn causes the delaying of the cells causing setup and hold violations. Hold violations cannot be fixed once the chip is fabricated. There are two types of IR drop analysis namely: Static IR drop analysis : • Calculates the average voltage drop of entire design assuming current drawn across is constant. • As average current is calculated this analysis depends on time period. This analysis is good for signoff checks in older technology.

• Dynamic IR drop analysis : • Depends on switching activity of the logic. • Is vector dependent . • Less dependent on clock period as depends on instantaneous current. • Analysis of peak current demand and highly localized cells.

• Methods to reduce IR drop : • Robust power mesh– Initial power grid is made based on static IR analysis due to late availability of switching activity. If there is IR drop due to some of the clustered cells then adding a strip will make the power mesh more robust. • De-cap– These are decoupling capacitors which are spread across the high switching region to maintain the voltage. • Spacing– If clock cells are clustered and causing IR drop, then by spacing them apart near to different power rails will reduce the IR drop. While shifting the cell to next power rail, it should be made sure that the power rail is not driving many cells, because adding another cell may give IR drop. • Reducing load– Cells driving more load will be drawing more current. Hence reducing load will reduce IR drop. • Downsizing– Cells of smaller size will draw less current. But the transition of cells should not become worse. • The number of power switches can be increased to reduce IR drop • It should be made sure that all the power pins of macros are properly connected to the power rails.

Execution

1. Go to Verification --> LVS --> Setup and Run and then the Dialog will appear.

2. LVS Setup box will appear. Keep the options default but if in case any options are not selected, then select them accordingly.

Check for Layer map file from Custom options tab as shown below if it is not selected by default.

3. If no errors then VUE (Visualization User Environment) window will appear saying the layout is LVS clean.

4. In the output directory many files are generated. The snapshot below shows the file from the text editor window which shows the LVS Clean status.

5. Now let's try to generate some errors to see how VUE window displays if any error occurs. Here, I have tried to change the W value of pmos which doesn't match with the schematic W value of pmos. Hence, It much generate LVS errors.

6. Now once again try to run LVS, VUE window will generate the errors as shown below:

7. You may check the errors description and try to correct them by looking into the LVS Errors tab in VUE. You can double click on the errors in the error list and check for where the error has occurred. In this case, It clearly shows that there is a mismatch error.

NOTE : When you edit any properties in Layout editor and save it that doesn't match with the Schematic editor. You can observe that there is a red mark on M1 in Design Navigator. So, you can look into that.

<img width="953" alt="step-17-LVS-4-error-4-grey color indication" src="https://user-images.githubusercontent.com/83152452/206909688-31d1e8ff-b125-4cdc-87c9-57037672ca3d.png">

XOR

• Compares and reports differences among polygons, edges, and/or text in two layout databases
• Comparison methods: XOR (default), NOT, or OUTSIDE
• Supported layout formats: OpenAccess (default), GDSII, OASIS
• Checking Area: Design – complete layout Viewport – selected viewport in layout Region – allows user to enter bbox coordinates from layout

Execution

1. You can go to Verification --> LVL --> Setup and Run from the Layout editor window. Here XOR operation is implemented on similar cells.

2. As you can see that there were no dissimilarities found in these two cells as they are the same, this was expected.

3. Once again run the LVL operation. Here XOR operation is implemented on dissimilar cells.

4. As you can see that there are many violations found in these two cells as they are not the same, this was also expected.

Acknowledgements

• Synopsys
• Kunal Ghosh, Co-founder, VSD Corp. Pvt. Ltd.

Author

• A Devipriya, B.E (Electronics and Communication Engineering), Bangalore - adevipriya1900@gmail.com

References

• Synopsys
• Emad-H
• VLSI Design Cycle - GeeksforGeeks
• ASIC Physical Design Flow - VLSIFacts
• CMOS Inverter : Circuit, Working, Characteristics & Its Applications (elprocus.com)