SEED-FPGA

8-bit Serialized Architecture of SEED Block Cipher for Constrained Devices

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This source is dedicated to the research paper entitled "8-bit Serialized Architecture of SEED Block Cipher for Constrained Devices" on IET Circuits, Devices & Systems journal

Authors : Filippos Pirpilidis, Lampros Pyrgas and Paris Kitsos
Institute: University of the Peloponnese
Department: Electrical and Computer Engineering

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This source is distributed in the hope that it will be useful, but WITHOUT ANY WARRANTY.

PLEASE CITE THIS PAPER IF YOU USE THIS CODE

Pirpilidis, F., Pyrgas, L. and Kitsos, P. (2020), 8‐bit serialised architecture of SEED block cipher for constrained devices. IET Circuits Devices Syst., 14: 316-321. https://doi.org/10.1049/iet-cds.2018.5354

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