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  1. dynamatic dynamatic Public

    DHLS (Dynamic High-Level Synthesis) compiler based on MLIR

    C++ 63 19

  2. fpga19-MOMS fpga19-MOMS Public

    VHDL 13 4

  3. fpl20-placement fpl20-placement Public

    Python 4 2

  4. fpl19-DynaBurst fpl19-DynaBurst Public

    VHDL 4 4

  5. fpga23-straight-lsq-interface fpga23-straight-lsq-interface Public

    This repository holds the source code, benchmarks and results of the work presented in the paper entitled "Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits".

    Verilog 4

  6. fpl21-avalanche fpl21-avalanche Public

    Python 3 2

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Showing 10 of 12 repositories
  • dynamatic Public

    DHLS (Dynamic High-Level Synthesis) compiler based on MLIR

    EPFL-LAP/dynamatic’s past year of commit activity
  • HardCilk Public
    EPFL-LAP/HardCilk’s past year of commit activity
    Verilog 0 GPL-3.0 0 0 0 Updated Nov 18, 2024
  • Polygeist Public Forked from llvm/Polygeist

    C/C++ frontend for MLIR. Also features polyhedral optimizations, parallel optimizations, and more!

    EPFL-LAP/Polygeist’s past year of commit activity
    C++ 1 118 0 0 Updated Feb 4, 2024
  • circt Public Forked from llvm/circt

    Circuit IR Compilers and Tools

    EPFL-LAP/circt’s past year of commit activity
    C++ 0 310 0 0 Updated Jan 18, 2024
  • fpga24-more-ooo Public

    This repository holds the source code, benchmarks and results of the work presented in the "Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits" paper, which allows for new levels of out-of-order execution in dataflow circuits that are not supported by prior work.

    EPFL-LAP/fpga24-more-ooo’s past year of commit activity
    C++ 2 MIT 0 0 0 Updated Jan 6, 2024
  • EPFL-LAP/fpga23-regularity’s past year of commit activity
    Python 2 MIT 0 0 0 Updated Jan 2, 2023
  • fpga23-straight-lsq-interface Public

    This repository holds the source code, benchmarks and results of the work presented in the paper entitled "Straight to the Queue: Fast Load-Store Queue Allocation in Dataflow Circuits".

    EPFL-LAP/fpga23-straight-lsq-interface’s past year of commit activity
    Verilog 4 MIT 0 0 0 Updated Dec 8, 2022
  • EPFL-LAP/fpl21-avalanche’s past year of commit activity
    Python 3 MIT 2 0 0 Updated Aug 23, 2021
  • EPFL-LAP/fpga21-scaled-tech’s past year of commit activity
    Python 1 MIT 4 0 0 Updated Jul 14, 2021
  • EPFL-LAP/fpl19-DynaBurst’s past year of commit activity
    VHDL 4 MIT 4 0 0 Updated Dec 3, 2020

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