Merge pull request #221 from rahulp13/sky130-dev

Added IPs and subcircuits, fixed path issues

INSTALL

@@ -14,7 +14,7 @@ Table of contents
 
    	i.      After downloading eSim, extract it using: 
 
-   		       $ unzip eSim-2.2.zip
+   		       $ unzip eSim-2.3.zip
 
    	ii.     Now change directories in to the top-level eSim directory (where this INSTALL file can be found).
 

README.md

@@ -10,7 +10,7 @@
 
 ## eSim
 
-[eSim](https://esim.fossee.in/) is an open source EDA tool for circuit design, simulation, analysis and PCB design, developed by [FOSSEE Team](https://www.fossee.in/) at [IIT Bombay](http://www.iitb.ac.in/).
+[eSim](https://esim.fossee.in/) is an open source EDA tool for circuit design, simulation, analysis and PCB design, developed by [FOSSEE Team](https://www.fossee.in/) at [IIT Bombay](https://www.iitb.ac.in/).
 It is an integrated tool build using open source softwares such as KiCad, Ngspice and GHDL.
 
 ## Releases and Installation
@@ -27,18 +27,19 @@ To use eSim on your machine having above distributions, please refer to link [he
 * Perform Circuit Design.
 * Perform Simulation.
 * Perform Layout Design.
-* Model builder and Subcircuit builder.
+* Model and Subcircuit builder.
 * Support for Mixed-Signal Simulations including Microcontrollers.
-* eSim has been successfully ported to low cost FOSSEE [laptop](http://laptop.fossee.in)
+* eSim has been successfully ported to low cost FOSSEE [laptop](https://laptop.fossee.in/)
 
 ## Open-Source Softwares Used
 * [Python](https://www.python.org/)
 * [KiCad](https://www.kicad.org/)
-* [Makerchip](https://www.makerchip.com/)
 * [NGHDL](https://github.com/fossee/nghdl/)
+* [Makerchip](https://www.makerchip.com/)
+* [SkyWater SKY130 PDK](https://skywater-pdk.rtfd.io/)
 
 ## eSim Manual
-To know everything about eSim, how it works and it's feature please download the manual from [here](https://static.fossee.in/esim/manuals/eSim_Manual_2.2.pdf)
+To know everything about eSim, how it works and it's feature please download the manual from [here](https://static.fossee.in/esim/manuals/eSim_Manual_2.3.pdf)
 
 ## Contact
 For any queries regarding eSim please write us on at this [email address](mailto:contact-esim@fossee.in).

VERSION

@@ -1 +1 @@
-2.2
+2.3

library/SubcircuitLibrary/SKY130_IP/avsd_opamp/.spiceinit

@@ -0,0 +1,6 @@
+
+set ngbehavior=hsa     ; set compatibility for reading PDK libs
+set ng_nomodcheck      ; don't check the model parameters 
+set num_threads=8      ; CPU hardware threads available
+option noinit          ; don't print operating point data
+optran 0 0 0 100p 2n 0 ; don't use dc operating point, but transient op)

library/SubcircuitLibrary/SKY130_IP/avsd_opamp/avsd_opamp.sub

@@ -0,0 +1,18 @@
+.subckt avsd_opamp vdd vss in1 in2 out2 gnd 
+* Stage 1 - Differential amplifier
+xm1 net-_m1-pad1_ in1 net-_m1-pad3_ net-_m1-pad3_ sky130_fd_pr__nfet_01v8 l=1 w=1.79
+xm2 out1 in2 net-_m1-pad3_ net-_m1-pad3_ sky130_fd_pr__nfet_01v8 l=1 w=1.79
+xm3 net-_m1-pad1_ net-_m1-pad1_ vdd vdd sky130_fd_pr__pfet_01v8 l=1 w=10
+xm4 out1 net-_m1-pad1_ vdd vdd sky130_fd_pr__pfet_01v8 l=1 w=10
+
+* Current Mirror
+xm5 net-_m1-pad3_ ref vss vss sky130_fd_pr__nfet_01v8 l=1 w=20
+xm6 ref ref vss vss sky130_fd_pr__nfet_01v8 l=1 w=10
+
+* Stage 2 - PMOS Common Source Amplifier
+xm7 out2 out1 vdd vdd sky130_fd_pr__pfet_01v8 l=1 w=62.83
+xm8 out2 ref vss vss sky130_fd_pr__nfet_01v8 l=1 w=62.83
+
+
+.ends
+

library/SubcircuitLibrary/SKY130_IP/avsdbgp_3v3_sky130_v2/.spiceinit

@@ -0,0 +1,6 @@
+
+set ngbehavior=hsa     ; set compatibility for reading PDK libs
+set ng_nomodcheck      ; don't check the model parameters 
+set num_threads=8      ; CPU hardware threads available
+option noinit          ; don't print operating point data
+optran 0 0 0 100p 2n 0 ; don't use dc operating point, but transient op)

library/SubcircuitLibrary/SKY130_IP/avsdbgp_3v3_sky130_v2/avsdbgp_3v3_sky130_v2.sub

@@ -0,0 +1,37 @@
+.subckt avsdbgp_3v3_sky130_v2 VPWR En GND VBGP
+*BGR circuit
+
+XM1 A C VPWR VPWR sky130_fd_pr__pfet_g5v0d10v5 l=5 w=20
+XM2 C C VPWR VPWR sky130_fd_pr__pfet_g5v0d10v5 l=5 w=20
+XM3 H C VPWR VPWR sky130_fd_pr__pfet_g5v0d10v5 l=5 w=20
+XM4 A A B GND sky130_fd_pr__nfet_g5v0d10v5 l=5 w=20
+XM5 C A D GND sky130_fd_pr__nfet_g5v0d10v5 l=5 w=20
+
+X6 GND GND I GND sky130_fd_pr__pnp_05v5_W3p40L3p40 M=1
+X7 GND GND E GND sky130_fd_pr__pnp_05v5_W3p40L3p40 M=8
+X8 GND GND F GND sky130_fd_pr__pnp_05v5_W3p40L3p40 M=1
+
+*Start-up circuit
+
+XM9 C G GND GND sky130_fd_pr__nfet_g5v0d10v5 l=5 w=20
+XM10 G A GND GND sky130_fd_pr__nfet_g5v0d10v5 l=1 w=20
+
+*Enable circuit
+
+XM11 B En Vx GND sky130_fd_pr__nfet_g5v0d10v5 l=5 w=20
+XM12 D En Vy GND sky130_fd_pr__nfet_g5v0d10v5 l=5 w=20
+XM13 H En Vz GND sky130_fd_pr__nfet_g5v0d10v5 l=5 w=20
+XM14 K En G GND sky130_fd_pr__nfet_g5v0d10v5 l=5 w=20
+
+R1 J E 30K
+R2 F VBGP 273K
+R3 GND VBGP 100MEG
+R4 VPWR Vw 200K
+
+Vsrc Vx I DC 0V
+Vsrc1 Vy J DC 0V
+Vsrc2 Vz VBGP DC 0V
+Vsrc3 Vw K DC 0V
+
+.ends  avsdbgp_3v3_sky130_v2 
+

library/SubcircuitLibrary/SKY130_IP/avsdcmp_3v3_sky130/.spiceinit

@@ -0,0 +1,6 @@
+
+set ngbehavior=hsa     ; set compatibility for reading PDK libs
+set ng_nomodcheck      ; don't check the model parameters 
+set num_threads=8      ; CPU hardware threads available
+option noinit          ; don't print operating point data
+optran 0 0 0 100p 2n 0 ; don't use dc operating point, but transient op)

library/SubcircuitLibrary/SKY130_IP/avsdcmp_3v3_sky130/avsdcmp_3v3_sky130.sub

@@ -0,0 +1,24 @@
+.subckt avsdcmp_3v3_sky130 VCC EN INP INN VOUT GND
+Ihyst VCC net4 pwl 0 0 20u 0 21u 0.2u 40u 0.2u 41u 0.8u 60u 0.8u 61u 10u 100u 10u
+
+XM2 VDIFF net1 VCC VCC sky130_fd_pr__pfet_g5v0d10v5 L=1 W=1 
+XM1 net1 net1 VCC VCC sky130_fd_pr__pfet_g5v0d10v5 L=1 W=1 
+XM12 VOUT2 VOUT1 VCC VCC sky130_fd_pr__pfet_g5v0d10v5 L=0.5 W=4 
+XM10 VOUT1 VDIFF VCC VCC sky130_fd_pr__pfet_g5v0d10v5 L=0.5 W=6 
+LOAD VOUT GND 10M m=1
+XM16 VOUT VOUT2 VCC VCC sky130_fd_pr__pfet_g5v0d10v5 L=0.5 W=4 
+XM22 VOUT2 EN VCC VCC sky130_fd_pr__pfet_g5v0d10v5 L=0.5 W=4 
+XM20 VOUT VOUT2 GND GND sky130_fd_pr__nfet_g5v0d10v5 L=0.5 W=2 
+XM17 net5 EN GND GND sky130_fd_pr__nfet_g5v0d10v5 L=0.5 W=2 
+XM13 VOUT2 VOUT1 net5 GND sky130_fd_pr__nfet_g5v0d10v5 L=0.5 W=2 
+XM11 VOUT1 VCC GND GND sky130_fd_pr__nfet_g5v0d10v5 L=0.5 W=0.5 
+XM7 net3 net4 GND GND sky130_fd_pr__nfet_g5v0d10v5 L=0.5 W=0.5 
+XM18 net4 net4 GND GND sky130_fd_pr__nfet_g5v0d10v5 L=0.5 W=0.5 
+XM6 net1 VOUT2 net3 GND sky130_fd_pr__nfet_g5v0d10v5 L=0.5 W=2 
+XM8 VDIFF VOUT1 net3 GND sky130_fd_pr__nfet_g5v0d10v5 L=0.5 W=2 
+XM5 net2 VCC GND GND sky130_fd_pr__nfet_g5v0d10v5 L=1 W=0.5 
+XM3 net1 INN net2 GND sky130_fd_pr__nfet_g5v0d10v5 L=0.5 W=1 
+XM4 VDIFF INP net2 GND sky130_fd_pr__nfet_g5v0d10v5 L=0.5 W=1 
+
+.ends avsdcmp_3v3_sky130 
+

library/SubcircuitLibrary/SKY130_IP/avsddac_3v3_sky130_v2/.spiceinit

@@ -0,0 +1,6 @@
+
+set ngbehavior=hsa     ; set compatibility for reading PDK libs
+set ng_nomodcheck      ; don't check the model parameters 
+set num_threads=8      ; CPU hardware threads available
+option noinit          ; don't print operating point data
+optran 0 0 0 100p 2n 0 ; don't use dc operating point, but transient op)

library/SubcircuitLibrary/SKY130_IP/avsddac_3v3_sky130_v2/10bit_DAC.cir.out

@@ -0,0 +1,34 @@
+* c:\users\91809\esim-workspace\10bit_dac\10bit_dac.cir
+
+.include 9bit_DAC.sub
+.include switch.sub
+
+x1 /vrefh net-_x1-pad2_ /d0 /d1 /d2 /d3 /d4 /d5 /d6 /d7 /d8 /vdd net-_x1-pad13_ 9bit_DAC
+x2 net-_x1-pad2_ /vrefl /d0 /d1 /d2 /d3 /d4 /d5 /d6 /d7 /d8 /vdd net-_x2-pad13_ 9bit_DAC
+x3 /d9 /vdd net-_x1-pad13_ net-_x2-pad13_ /vout switch
+* u1  /vrefh /vrefl /d0 /d1 /d2 /d3 /d4 /d5 /d6 /d7 /d8 /d9 /vdd /vout port
+
+
+Vdd /vdd 0 3.3
+Vd0 /d0 0 pulse(0 1.8 0ns 0 0 5us 10us)
+Vd1 /d1 0 pulse(0 1.8 0ns 0 0 10us 20us)
+Vd2 /d2 0 pulse(0 1.8 0ns 0 0 20us 40us)
+Vd3 /d3 0 pulse(0 1.8 0ns 0 0 40us 80us)
+Vd4 /d4 0 pulse(0 1.8 0ns 0 0 80us 160us)
+Vd5 /d5 0 pulse(0 1.8 0ns 0 0 160us 320us)
+Vd6 /d6 0 pulse(0 1.8 0ns 0 0 320us 640us)
+Vd7 /d7 0 pulse(0 1.8 0ns 0 0 640us 1280us)
+Vd8 /d8 0 pulse(0 1.8 0ns 0 0 1280us 2560us)
+Vd9 /d9 0 pulse(0 1.8 0ns 0 0 2560us 5120us)
+Vrefh /vrefh 0 3.3
+Vrefl /vrefl 0 0
+
+.tran 50us 5120us
+
+* Control Statements 
+.control
+run
+print allv > plot_data_v.txt
+print alli > plot_data_i.txt
+.endc
+.end

library/SubcircuitLibrary/SKY130_IP/avsddac_3v3_sky130_v2/10bit_DAC0.cir.out

@@ -0,0 +1,32 @@
+* c:\users\91809\esim-workspace\10bit_dac\10bit_dac.cir
+
+.include 9bit_DAC.sub
+.include switch.sub
+x1 vrefh net-_x1-pad2_ d0 d1 d2 d3 d4 d5 d6 d7 d8 vdd net-_x1-pad13_ 9bit_DAC
+x2 net-_x1-pad2_ vrefl d0 d1 d2 d3 d4 d5 d6 d7 d8 vdd net-_x2-pad13_ 9bit_DAC
+x3 d9 vdd net-_x1-pad13_ net-_x2-pad13_ vout switch
+* u1  /vrefh /vrefl /d0 /d1 /d2 /d3 /d4 /d5 /d6 /d7 /d8 /d9 /vdd /vout port
+
+
+Vdd vdd 0 3.3
+Vd0 d0 0 1.8
+Vd1 d1 0 1.8
+Vd2 d2 0 1.8
+Vd3 d3 0 1.8
+Vd4 d4 0 1.8
+Vd5 d5 0 1.8
+Vd6 d6 0 pulse(0 1.8 0ns 0 0 320us 640us)
+Vd7 d7 0 pulse(0 1.8 0ns 0 0 640us 1280us)
+Vd8 d8 0 pulse(0 1.8 0ns 0 0 1280us 2560us)
+Vd9 d9 0 pulse(0 1.8 0ns 0 0 2560us 5120us)
+Vrefh vrefh 0 3.3
+Vrefl vrefl 0 0
+
+.tran 320us 5120us
+
+* Control Statements 
+.control
+run
+plot vout
+.endc
+.end

library/SubcircuitLibrary/SKY130_IP/avsddac_3v3_sky130_v2/10bit_DAC1.cir.out

@@ -0,0 +1,32 @@
+* c:\users\91809\esim-workspace\10bit_dac\10bit_dac.cir
+
+.include 9bit_DAC.sub
+.include switch.sub
+x1 vrefh net-_x1-pad2_ d0 d1 d2 d3 d4 d5 d6 d7 d8 vdd net-_x1-pad13_ 9bit_DAC
+x2 net-_x1-pad2_ vrefl d0 d1 d2 d3 d4 d5 d6 d7 d8 vdd net-_x2-pad13_ 9bit_DAC
+x3 d9 vdd net-_x1-pad13_ net-_x2-pad13_ vout switch
+* u1  /vrefh /vrefl /d0 /d1 /d2 /d3 /d4 /d5 /d6 /d7 /d8 /d9 /vdd /vout port
+
+
+Vdd vdd 0 3.3
+Vd0 d0 0 pulse(0 1.8 0ns 0 0 5us 10us)
+Vd1 d1 0 pulse(0 1.8 0ns 0 0 10us 20us)
+Vd2 d2 0 pulse(0 1.8 0ns 0 0 20us 40us)
+Vd3 d3 0 pulse(0 1.8 0ns 0 0 40us 80us)
+Vd4 d4 0 pulse(0 1.8 0ns 0 0 80us 160us)
+Vd5 d5 0 pulse(0 1.8 0ns 0 0 160us 320us)
+Vd6 d6 0 pulse(0 1.8 0ns 0 0 320us 640us)
+Vd7 d7 0 pulse(0 1.8 0ns 0 0 640us 1280us)
+Vd8 d8 0 pulse(0 1.8 0ns 0 0 1280us 2560us)
+Vd9 d9 0 pulse(0 1.8 0ns 0 0 2560us 5120us)
+Vrefh vrefh 0 3.3
+Vrefl vrefl 0 0
+
+.tran 50us 5120us
+
+* Control Statements 
+.control
+run
+plot vout
+.endc
+.end

library/SubcircuitLibrary/SKY130_IP/avsddac_3v3_sky130_v2/2bit_DAC.sub

@@ -0,0 +1,14 @@
+* Subcircuit 2bit_DAC
+.subckt 2bit_DAC /vrefh /vrefl /d0 /d1 /vdd /vout 
+* c:\fossee\esim\library\subcircuitlibrary\2bit_dac\2bit_dac.cir
+.include switch.sub
+r1  /vrefh net-_r1-pad2_ 250
+r2  net-_r1-pad2_ net-_r2-pad2_ 250
+r3  net-_r2-pad2_ net-_r3-pad2_ 250
+r4  net-_r3-pad2_ /vrefl 250
+x1 /d0 /vdd net-_r1-pad2_ net-_r2-pad2_ net-_x1-pad5_ switch
+x2 /d0 /vdd net-_r3-pad2_ /vrefl net-_x2-pad5_ switch
+x3 /d1 /vdd net-_x1-pad5_ net-_x2-pad5_ /vout switch
+* Control Statements
+
+.ends 2bit_DAC

library/SubcircuitLibrary/SKY130_IP/avsddac_3v3_sky130_v2/3bit_DAC.sub

@@ -0,0 +1,11 @@
+* Subcircuit 3bit_DAC
+.subckt 3bit_DAC /vrefh /vrefl /d0 /d1 /d2 /vdd /vout 
+* c:\fossee\esim\library\subcircuitlibrary\3bit_dac\3bit_dac.cir
+.include 2bit_DAC.sub
+.include switch.sub
+x1 /vrefh net-_x1-pad2_ /d0 /d1 /vdd net-_x1-pad6_ 2bit_DAC
+x2 net-_x1-pad2_ /vrefl /d0 /d1 /vdd net-_x2-pad6_ 2bit_DAC
+x3 /d2 /vdd net-_x1-pad6_ net-_x2-pad6_ /vout switch
+* Control Statements
+
+.ends 3bit_DAC

library/SubcircuitLibrary/SKY130_IP/avsddac_3v3_sky130_v2/4bit_DAC.sub

@@ -0,0 +1,11 @@
+* Subcircuit 4bit_DAC
+.subckt 4bit_DAC /vrefh /vrefl /d0 /d1 /d2 /d3 /vdd /vout 
+* c:\fossee\esim\library\subcircuitlibrary\4bit_dac\4bit_dac.cir
+.include 3bit_DAC.sub
+.include switch.sub
+x1 /vrefh net-_x1-pad2_ /d0 /d1 /d2 /vdd net-_x1-pad7_ 3bit_DAC
+x2 net-_x1-pad2_ /vrefl /d0 /d1 /d2 /vdd net-_x2-pad7_ 3bit_DAC
+x3 /d3 /vdd net-_x1-pad7_ net-_x2-pad7_ /vout switch
+* Control Statements
+
+.ends 4bit_DAC

library/SubcircuitLibrary/SKY130_IP/avsddac_3v3_sky130_v2/5bit_DAC.sub

@@ -0,0 +1,11 @@
+* Subcircuit 5bit_DAC
+.subckt 5bit_DAC /vrefh /vrefl /d0 /d1 /d2 /d3 /d4 /vdd /vout 
+* c:\fossee\esim\library\subcircuitlibrary\5bit_dac\5bit_dac.cir
+.include switch.sub
+.include 4bit_DAC.sub
+x1 /vrefh net-_x1-pad2_ /d0 /d1 /d2 /d3 /vdd net-_x1-pad8_ 4bit_DAC
+x2 net-_x1-pad2_ /vrefl /d0 /d1 /d2 /d3 /vdd net-_x2-pad8_ 4bit_DAC
+x3 /d4 /vdd net-_x1-pad8_ net-_x2-pad8_ /vout switch
+* Control Statements
+
+.ends 5bit_DAC

library/SubcircuitLibrary/SKY130_IP/avsddac_3v3_sky130_v2/5bit_DACa.sub

@@ -0,0 +1,70 @@
+* Subcircuit 5bit_DACa
+.subckt 5bit_DACa /vrefh /vrefl /d0 /d1 /d2 /d3 /d4 /vdd /vout 
+* c:\fossee\esim\library\subcircuitlibrary\5bit_daca\5bit_daca.cir
+.include switch.sub
+r1  /vrefh net-_r1-pad2_ 250
+r2  net-_r1-pad2_ net-_r2-pad2_ 250
+r3  net-_r2-pad2_ net-_r3-pad2_ 250
+r4  net-_r3-pad2_ net-_r4-pad2_ 250
+r5  net-_r4-pad2_ net-_r5-pad2_ 250
+r6  net-_r5-pad2_ net-_r6-pad2_ 250
+r7  net-_r6-pad2_ net-_r7-pad2_ 250
+r8  net-_r7-pad2_ net-_r8-pad2_ 250
+r9  net-_r8-pad2_ net-_r10-pad1_ 250
+r10  net-_r10-pad1_ net-_r10-pad2_ 250
+r11  net-_r10-pad2_ net-_r11-pad2_ 250
+r12  net-_r11-pad2_ net-_r12-pad2_ 250
+r13  net-_r12-pad2_ net-_r13-pad2_ 250
+r14  net-_r13-pad2_ net-_r14-pad2_ 250
+r15  net-_r14-pad2_ net-_r15-pad2_ 250
+r16  net-_r15-pad2_ net-_r16-pad2_ 250
+r32  /vrefl net-_r31-pad1_ 250
+r31  net-_r31-pad1_ net-_r30-pad1_ 250
+r30  net-_r30-pad1_ net-_r29-pad1_ 250
+r29  net-_r29-pad1_ net-_r28-pad1_ 250
+r28  net-_r28-pad1_ net-_r27-pad1_ 250
+r27  net-_r27-pad1_ net-_r26-pad1_ 250
+r26  net-_r26-pad1_ net-_r25-pad1_ 250
+r25  net-_r25-pad1_ net-_r24-pad1_ 250
+r24  net-_r24-pad1_ net-_r23-pad1_ 250
+r23  net-_r23-pad1_ net-_r22-pad1_ 250
+r22  net-_r22-pad1_ net-_r21-pad1_ 250
+r21  net-_r21-pad1_ net-_r20-pad1_ 250
+r20  net-_r20-pad1_ net-_r19-pad1_ 250
+r19  net-_r19-pad1_ net-_r18-pad1_ 250
+r18  net-_r18-pad1_ net-_r17-pad1_ 250
+r17  net-_r17-pad1_ net-_r16-pad2_ 250
+x1 /d0 /vdd net-_r1-pad2_ net-_r2-pad2_ net-_x1-pad5_ switch
+x2 /d0 /vdd net-_r3-pad2_ net-_r4-pad2_ net-_x11-pad4_ switch
+x3 /d0 /vdd net-_r5-pad2_ net-_r6-pad2_ net-_x12-pad3_ switch
+x4 /d0 /vdd net-_r7-pad2_ net-_r8-pad2_ net-_x12-pad4_ switch
+x5 /d0 /vdd net-_r10-pad1_ net-_r10-pad2_ net-_x13-pad3_ switch
+x6 /d0 /vdd net-_r11-pad2_ net-_r12-pad2_ net-_x13-pad4_ switch
+x7 /d0 /vdd net-_r13-pad2_ net-_r14-pad2_ net-_x14-pad3_ switch
+x8 /d0 /vdd net-_r15-pad2_ net-_r16-pad2_ net-_x14-pad4_ switch
+x9 /d0 /vdd net-_r17-pad1_ net-_r18-pad1_ net-_x15-pad3_ switch
+x10 /d0 /vdd net-_r19-pad1_ net-_r20-pad1_ net-_x10-pad5_ switch
+x110 /d0 /vdd net-_r21-pad1_ net-_r22-pad1_ net-_x110-pad5_ switch
+x120 /d0 /vdd net-_r23-pad1_ net-_r24-pad1_ net-_x120-pad5_ switch
+x130 /d0 /vdd net-_r25-pad1_ net-_r26-pad1_ net-_x130-pad5_ switch
+x140 /d0 /vdd net-_r27-pad1_ net-_r28-pad1_ net-_x140-pad5_ switch
+x150 /d0 /vdd net-_r29-pad1_ net-_r30-pad1_ net-_x150-pad5_ switch
+x160 /d0 /vdd net-_r31-pad1_ /vrefl net-_x160-pad5_ switch
+x11 /d1 /vdd net-_x1-pad5_ net-_x11-pad4_ net-_x11-pad5_ switch
+x12 /d1 /vdd net-_x12-pad3_ net-_x12-pad4_ net-_x12-pad5_ switch
+x13 /d1 /vdd net-_x13-pad3_ net-_x13-pad4_ net-_x13-pad5_ switch
+x14 /d1 /vdd net-_x14-pad3_ net-_x14-pad4_ net-_x14-pad5_ switch
+x15 /d1 /vdd net-_x15-pad3_ net-_x10-pad5_ net-_x15-pad5_ switch
+x16 /d1 /vdd net-_x110-pad5_ net-_x120-pad5_ net-_x16-pad5_ switch
+x17 /d1 /vdd net-_x130-pad5_ net-_x140-pad5_ net-_x17-pad5_ switch
+x18 /d1 /vdd net-_x150-pad5_ net-_x160-pad5_ net-_x18-pad5_ switch
+x21 /d2 /vdd net-_x11-pad5_ net-_x12-pad5_ net-_x21-pad5_ switch
+x24 /d2 /vdd net-_x17-pad5_ net-_x18-pad5_ net-_x24-pad5_ switch
+x22 /d2 /vdd net-_x13-pad5_ net-_x14-pad5_ net-_x22-pad5_ switch
+x23 /d2 /vdd net-_x15-pad5_ net-_x16-pad5_ net-_x23-pad5_ switch
+x31 /d3 /vdd net-_x21-pad5_ net-_x22-pad5_ net-_x31-pad5_ switch
+x32 /d3 /vdd net-_x23-pad5_ net-_x24-pad5_ net-_x32-pad5_ switch
+x41 /d4 /vdd net-_x31-pad5_ net-_x32-pad5_ /vout switch
+* Control Statements
+
+.ends 5bit_DACa

library/SubcircuitLibrary/SKY130_IP/avsddac_3v3_sky130_v2/6bit_DAC.sub

@@ -0,0 +1,11 @@
+* Subcircuit 6bit_DAC
+.subckt 6bit_DAC /vrefh /vrefl /d0 /d1 /d2 /d3 /d4 /d5 /vdd /vout 
+* c:\fossee\esim\library\subcircuitlibrary\6bit_dac\6bit_dac.cir
+.include switch.sub
+.include 5bit_DACa.sub
+x1 /vrefh net-_x1-pad2_ /d0 /d1 /d2 /d3 /d4 /vdd net-_x1-pad9_ 5bit_DACa
+x2 net-_x1-pad2_ /vrefl /d0 /d1 /d2 /d3 /d4 /vdd net-_x2-pad9_ 5bit_DACa
+x3 /d5 /vdd net-_x1-pad9_ net-_x2-pad9_ /vout switch
+* Control Statements
+
+.ends 6bit_DAC