apio build refactoring

.vscode/launch.json

@@ -6,7 +6,7 @@
             "type": "debugpy",
             "request": "launch",
             "program": "${file}",
-            "args": ["build", "-p", "ledon2"],
+            "args": ["build","--top-module","caca"],
             "console": "internalConsole",
             "justMyCode": true,
             //-- Change to the folder with the example to test

apio/commands/boards.py

@@ -8,7 +8,6 @@
 """Main implementation of APIO BOARDS command"""
 
 import click
-
 from apio.resources import Resources
 from apio import util
 
@@ -32,7 +31,6 @@
     "-f", f"--{FPGA}", is_flag=True, help="List all supported FPGA chips."
 )
 def cli(ctx, **kwargs):
-    # def cli(ctx, list_boards: bool, fpga: bool):
     """Manage FPGA boards."""
 
     # -- Extract the arguments

apio/commands/build.py

@@ -13,15 +13,32 @@
 from apio.managers.scons import SCons
 from apio import util
 
+# ------------------
+# -- CONSTANTS
+# ------------------
+CMD = "build"  # -- Comand name
+BOARD = "board"  # -- Option
+FPGA = "fpga"  # -- Option
+PACK = "pack"  # -- Option
+TYPE = "type"  # -- Option
+SIZE = "size"  # -- Option
+PROJECT_DIR = "project_dir"  # -- Option
+VERBOSE = "verbose"  # -- Option
+VERBOSE_YOSYS = "verbose_yosys"  # -- Option
+VERBOSE_PNR = "verbose_pnr"  # -- Option
+TOP_MODULE = "top_module"  # -- Option
+
 
 # R0913: Too many arguments (6/5)
 # pylint: disable=R0913
 # pylint: disable=W0622
 # pylint: disable=R0801
-@click.command("build", context_settings=util.context_settings())
+@click.command(CMD, context_settings=util.context_settings())
 @click.pass_context
-@click.option("-b", "--board", type=str, metavar="str", help="Set the board.")
-@click.option("--fpga", type=str, metavar="str", help="Set the FPGA.")
+@click.option(
+    "-b", f"--{BOARD}", type=str, metavar="str", help="Set the board."
+)
+@click.option(f"--{FPGA}", type=str, metavar="str", help="Set the FPGA.")
 @click.option(
     "--size", type=str, metavar="str", help="Set the FPGA type (1k/8k)."
 )
@@ -56,21 +73,21 @@
     metavar="str",
     help="Set the top level module (w/o .v ending) for build.",
 )
-def cli(
-    ctx,
-    board,
-    fpga,
-    pack,
-    type,
-    size,
-    project_dir,
-    verbose,
-    verbose_yosys,
-    verbose_pnr,
-    top_module,
-):
+def cli(ctx, **kwargs):
     """Synthesize the bitstream."""
 
+    # -- Extract the arguments
+    board = kwargs[BOARD]
+    fpga = kwargs[FPGA]
+    pack = kwargs[PACK]
+    _type = kwargs[TYPE]
+    size = kwargs[SIZE]
+    project_dir = kwargs[PROJECT_DIR]
+    verbose = kwargs[VERBOSE]
+    verbose_yosys = kwargs[VERBOSE_YOSYS]
+    verbose_pnr = kwargs[VERBOSE_PNR]
+    top_module = kwargs[TOP_MODULE]
+
     # The bitstream is generated from the source files (verilog)
     # by means of the scons tool
     # https://www.scons.org/documentation.html
@@ -84,7 +101,7 @@ def cli(
             "board": board,
             "fpga": fpga,
             "size": size,
-            "type": type,
+            "type": _type,
             "pack": pack,
             "verbose": {
                 "all": verbose,