Add --timing flag in apio lint (verilator)

FPGAwars · Mar 19, 2024 · 469dc49 · 469dc49
1 parent 3c5fcc6
commit 469dc49
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Showing 3 changed files with 3 additions and 2 deletions.
diff --git a/apio/resources/ecp5/SConstruct b/apio/resources/ecp5/SConstruct
@@ -324,7 +324,7 @@ if 'test' in COMMAND_LINE_TARGETS:
 
 # -- Verilator builder
 verilator = Builder(
-    action='verilator --lint-only -v {0}/ecp5/cells_sim.v {1} {2} {3} {4} $SOURCES'.format(
+    action='verilator --lint-only --timing -Wno-TIMESCALEMOD -v {0}/ecp5/cells_sim.v {1} {2} {3} {4} $SOURCES'.format(
         YOSYS_PATH,
         '-Wall' if VERILATOR_ALL else '',
         '-Wno-style' if VERILATOR_NO_STYLE else '',

diff --git a/apio/resources/ice40/SConstruct b/apio/resources/ice40/SConstruct
@@ -330,7 +330,7 @@ if 'test' in COMMAND_LINE_TARGETS:
 
 # -- Verilator builder
 verilator = Builder(
-    action='verilator --lint-only -Wno-TIMESCALEMOD {0} {1} {2} {3} $SOURCES'.format(
+    action='verilator --lint-only --timing -Wno-TIMESCALEMOD {0} {1} {2} {3} $SOURCES'.format(
         '-Wall' if VERILATOR_ALL else '',
         '-Wno-style' if VERILATOR_NO_STYLE else '',
         VERILATOR_PARAM_STR if VERILATOR_PARAM_STR else '',

diff --git a/test-examples/Radiona-ULX3S-12F/01-LEDs-buttons/apio.ini b/test-examples/Radiona-ULX3S-12F/01-LEDs-buttons/apio.ini
@@ -1,3 +1,4 @@
 [env]
 board = ulx3s-12f
+top-module = main