Added the possibility to indicate top module in upload option

FPGAwars · Oct 2, 2023 · e695bb0 · e695bb0
1 parent f99b255
commit e695bb0
Showing 1 changed file with 8 additions and 0 deletions.
diff --git a/apio/commands/upload.py b/apio/commands/upload.py
@@ -50,6 +50,12 @@
 @click.option(
     "--verbose-pnr", is_flag=True, help="Show the pnr output of the command."
 )
+@click.option(
+    "--top-module",
+    type=str,
+    metavar="top_module",
+    help="Set the top level module (w/o .v ending) for build.",
+)
 def cli(
     ctx,
     board,
@@ -61,6 +67,7 @@ def cli(
     verbose,
     verbose_yosys,
     verbose_pnr,
+    top_module,
 ):
     """Upload the bitstream to the FPGA."""
 
@@ -76,6 +83,7 @@ def cli(
                 "yosys": verbose_yosys,
                 "pnr": verbose_pnr,
             },
+            "top-module": top_module,
         },
         serial_port,
         ftdi_id,