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@testinguser
testinguser committed May 27, 2024
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Showing 1 changed file with 50 additions and 31 deletions.
81 changes: 50 additions & 31 deletions locale/translation.js
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Expand Up @@ -456,8 +456,7 @@ gettext('iCEBreaker');
gettext('iCESuger-1.5');
gettext('01-Mux-2-1-button-LED');
gettext('Constant bit 1');
gettext('System TFF: It toogles its output on every system cycle');
gettext('D Flip-flop (verilog implementation)');
gettext('Sys-TFF: System TFF: It toogles its output on every system cycle. Verilog implementation');
gettext('## Example: Manual testing of the 2-to-1 Mux\n\nThe LED is on (at its maximum bright) when the button is not pressed. \nWhen the button is pressed a 50 percent duty cycle signal is sent to the \nLED. The LED is on but less bright');
gettext('T-Flip flop');
gettext('50 percent duty cycle');
Expand All @@ -466,13 +465,15 @@ gettext('Channel 1');
gettext('Channel 0');
gettext('button for selecting the \nchannel to send to the LED');
gettext('**2-to-1 Mux**');
gettext('01-Mux-2-1-button-LED');
gettext('System TFF: It toogles its output on every system cycle');
gettext('D Flip-flop (verilog implementation)');
gettext('Parameter: Initial value');
gettext('System clock');
gettext('Input data');
gettext('# D Flip-Flop \n\nIt stores the input data that arrives at cycle n \nIts output is shown in the cycle n+1');
gettext('01-Mux-2-1-button-LED');
gettext('01-Mux-2-1-button-LED');
gettext('01-Mux-2-1-button-LED');
gettext('Constant bit 0');
gettext('01-Mux-2-1-button-LED');
gettext('2bits constant value: 3');
Expand Down Expand Up @@ -509,17 +510,17 @@ gettext('iCEBreaker');
gettext('iCESugar-1.5');
gettext('03-Mux-4-1-button-LED');
gettext('Button-tic: Configurable button that emits a tic when it is pressed');
gettext('Rising-edge detector. It generates a 1-period pulse (tic) when a rising edge is detected on the input');
gettext('Rising-edge detector. It generates a 1-period pulse (tic) when a rising edge is detected on the input. Block implementation');
gettext('System - D Flip-flop. Capture data every system clock cycle. Verilog implementation');
gettext('Configurable button (pull-up on/off. Not on/off)');
gettext('FPGA internal pull-up configuration on the input port');
gettext('Select positive or negative logic for the input (0=positive, 1=negative)');
gettext('Valor genérico constante, de 1 bits. Su valor se introduce como parámetro. Por defecto vale 0');
gettext('XOR gate: two bits input xor gate');
gettext('Remove the rebound on a mechanical switch');
gettext('1bit register (implemented in verilog)');
gettext('Edges detector. It generates a 1-period pulse (tic) when either a rising edge or a falling edge is detected on the input. Block implementation');
gettext('DFF. D Flip-flop. Verilog implementation');
gettext('16-bits Syscounter with reset');
gettext('DFF-rst-x16: 16 D flip-flops in paralell with reset');
gettext('DFF-rst-x04: Three D flip-flops in paralell with reset');
gettext('DFF-rst-x01: D Flip flop with reset input. When rst=1, the DFF is 0');
gettext('Bus16-Split-quarter: Split the 16-bits bus into four buses of the same size');
gettext('Bus16-Join-quarter: Join the four same buses into an 16-bits Bus');
gettext('Inc1-16bit: Increment a 16-bits number by one');
gettext('AdderK-16bit: Adder of 16-bit operand and 16-bit constant');
gettext('Generic: 16-bits generic constant');
Expand All @@ -528,23 +529,19 @@ gettext('Adder-8bits: Adder of two operands of 8 bits');
gettext('Adder-4bits: Adder of two operands of 4 bits');
gettext('Adder-1bit: Adder of two operands of 1 bit');
gettext('AdderC-1bit: Adder of two operands of 1 bit plus the carry in');
gettext('XOR gate: two bits input xor gate');
gettext('AdderC-4bits: Adder of two operands of 4 bits and Carry in');
gettext('AdderC-8bits: Adder of two operands of 8 bits and Carry in');
gettext('Edges detector. It generates a 1-period pulse (tic) when either a rising edge or a falling edge is detected on the input');
gettext('Sync 1-bit input with the system clock domain');
gettext('Select positive or negative logic for the input (0=positive, 1=negative)');
gettext('1-bit generic constant (0/1)');
gettext('16-Sys-reg-rst: 16 bits system register with reset. Verilog implementation');
gettext('Sync-x01: 1-bit input with the system clock domain (Verilog implementation)');
gettext('Counter-x02: 2-bits counter');
gettext('Generic component with clk input');
gettext('Reg: 1-Bit register');
gettext('Inc1-2bit: Increment a 2-bits number by one');
gettext('AdderK-2bit: Adder of 2-bit operand and 2-bit constant');
gettext('Adder-2bits: Adder of two operands of 2 bits');
gettext('02-Reg: 2 bits Register. Verilog implementation');
gettext('sysclk_div: Generate a signal from the division of the system clock by 2');
gettext('sysclk_div4: Generate a signal from the division of the system clock by 4');
gettext('2-bits Syscounter');
gettext('DFF-02: Two D flip-flops in paralell');
gettext('sysclk_div: Generate a signal from the division of the system clock by 2');
gettext('02-Sys-reg: 2 bits system register. Verilog implementation');
gettext('## Example: Manual testing of the 4-to-1 Mux\n\nFour signal with duty cycles of 100%, 50%, 25% and 0% are selected and displayed on \nLED7. When the button is pressed, the next channel is selected, starting from channel 0');
gettext('**4-to-1 Mux**');
gettext('### 25%');
Expand All @@ -563,33 +560,48 @@ gettext('Current signal \nstate');
gettext('Signal state in the previous \nclock cycle');
gettext('If the current signal is 1 and its value in \nthe previous clock cycle was 0, it means \nthat a rising edge has been detected! \nThe output es 1\n\nIn any other case the output is 0');
gettext('**Delay**: 0 clock cycles \n\nThere is no delay between the arrival of a rising edge \nand its detection');
gettext('# D Flip-Flop (system)\n\nIt stores the input data that arrives at cycle n \nIts output is shown in the cycle n+1');
gettext('Not connected');
gettext('Internal pull-up \n* 0: OFF\n* 1: ON');
gettext('Synchronization stage');
gettext('Normalization stage\n\n* 0: Wire\n* 1: signal inverted');
gettext('Debouncing stage');
gettext('### Pull-up parameter:\n\n0: No pull-up \n1: Pull-up activated');
gettext('Only an FPGA pin can \nbe connected here!!!');
gettext('The pull-up is connected \nby default');
gettext('When k=0, it works like a wire \n(The output is equal to the input) \nWhen k=1, it act as a not gate\n(The output is the inverse of the input)');
gettext('### Truth table for XOR\n\n| k | input | output | function |\n|---|-------|--------|----------|\n| 0 | 0 | 0 | wire |\n| 0 | 1 | 1 | wire |\n| 1 | 0 | 1 | Not |\n| 1 | 1 | 0 | Not |');
gettext('Edge detector');
gettext('Whenever there is a change in \nthe input, the counter is started');
gettext('If the counter reaches it maximum \nvalue, the input is considered stable \nand it is captured');
gettext('### Time calculation\n\nFor CLK=12MHZ, a 16-bit counter reaches its \nmaximum every 2 ** 16 * 1/F = 5.5ms aprox \nIF more time is needed for debouncing, \nuse a counter with more bits (17, 18...)');
gettext('## Debouncer \n\nA value is considered stable when \nthere is no changes during 5.5ms \naprox. When a value is stable it is \ncaptured on the output flip-flop');
gettext('Stable output');
gettext('Counter');
gettext('## Edges detector\n\nIt generates a 1-period pulse (tic) when an edge (Rising or falling) is detected on the \ninput signal');
gettext('The output is 1 if the current value is 1 and the \nprevious 0, or if the current value is 0 and the \nprevious 1\n');
gettext('In any other case the output is 0');
gettext('03-Mux-4-1-button-LED');
gettext('Rising-edge detector. It generates a 1-period pulse (tic) when a rising edge is detected on the input');
gettext('1bit register (implemented in verilog)');
gettext('DFF-rst-x16: 16 D flip-flops in paralell with reset');
gettext('DFF-rst-x04: Three D flip-flops in paralell with reset');
gettext('DFF-rst-x01: D Flip flop with reset input. When rst=1, the DFF is 0');
gettext('Bus16-Split-quarter: Split the 16-bits bus into four buses of the same size');
gettext('Bus16-Join-quarter: Join the four same buses into an 16-bits Bus');
gettext('Edges detector. It generates a 1-period pulse (tic) when either a rising edge or a falling edge is detected on the input');
gettext('Sync 1-bit input with the system clock domain');
gettext('1-bit generic constant (0/1)');
gettext('Generic component with clk input');
gettext('Reg: 1-Bit register');
gettext('DFF-02: Two D flip-flops in paralell');
gettext('Initial value');
gettext('Reset input: Active high \nWhen rst = 1, the DFF is reset to 0');
gettext('Data input');
gettext('Initial default \nvalue: 0');
gettext('## Edges detector\n\nIt generates a 1-period pulse (tic) when an edge (Rising or falling) is detected on the \ninput signal');
gettext('The output is 1 if the current value is 1 and the \nprevious 0, or if the current value is 0 and the \nprevious 1\n');
gettext('In any other case the output is 0');
gettext('When k=0, it works like a wire \n(The output is equal to the input) \nWhen k=1, it act as a not gate\n(The output is the inverse of the input)');
gettext('### Truth table for XOR\n\n| k | input | output | function |\n|---|-------|--------|----------|\n| 0 | 0 | 0 | wire |\n| 0 | 1 | 1 | wire |\n| 1 | 0 | 1 | Not |\n| 1 | 1 | 0 | Not |');
gettext('Mux 2-1');
gettext('D Flip-flip\n(System)');
gettext('03-Mux-4-1-button-LED');
gettext('03-Mux-4-1-button-LED');
gettext('Button-tic: Configurable button that emits a tic when it is pressed. ECP5 FPGA Family');
gettext('Configurable button (pull-up on/off. Not on/off). ECP5 FPGA family');
gettext('03-Mux-4-1-button-LED');
Expand Down Expand Up @@ -618,42 +630,47 @@ gettext('iCEBreaker');
gettext('iCESugar-1.5');
gettext('05-Mux-8-1-button-LED');
gettext('Counter-x03: 3-bits counter');
gettext('Reg-x03: 3-bits register');
gettext('Inc1-3bit: Increment a 3-bits number by one');
gettext('AdderK-3bit: Adder of 3-bit operand and 3-bit constant');
gettext('Generic: 3-bits generic constant (0-7)');
gettext('Adder-3bits: Adder of two operands of 3 bits');
gettext('03-Reg: 3 bits Register. Verilog implementation');
gettext('sysclk_div8: Generate a signal from the division of the system clock by 8');
gettext('3-bits Syscounter');
gettext('DFF-03: Three D flip-flops in paralell');
gettext('03-Sys-reg: 3 bits system register. Verilog implementation');
gettext('sysclk_div16: Generate a signal from the division of the system clock by 16');
gettext('4-bits Syscounter');
gettext('DFF-04: Three D flip-flops in paralell');
gettext('Inc1-4bit: Increment a 4-bits number by one');
gettext('AdderK-4bit: Adder of 4-bit operand and 4-bit constant');
gettext('04-Sys-reg: 4 bits system register. Verilog implementation');
gettext('sysclk_div32: Generate a signal from the division of the system clock by 32');
gettext('5-bits Syscounter');
gettext('DFF-05: five D flip-flops in paralell');
gettext('Inc1-5bit: Increment a 5-bits number by one');
gettext('AdderK-5bit: Adder of 5-bit operand and 5-bit constant');
gettext('Adder-5bits: Adder of two operands of 5 bits');
gettext('Generic: 5-bits generic constant (0-31)');
gettext('05-Sys-reg: 5 bits system register. Verilog implementation');
gettext('sysclk_div64: Generate a signal from the division of the system clock by 64');
gettext('6-bits Syscounter with reset');
gettext('DFF-rst-x06: Six D flip-flops in paralell with reset');
gettext('DFF-rst-x02: Two D flip-flops in paralell with reset');
gettext('Inc1-6bit: Increment a 6-bits number by one');
gettext('AdderK-6bit: Adder of 6-bit operand and 6-bit constant');
gettext('Adder-6bits: Adder of two operands of 6 bits');
gettext('Bus6-Join-1-5: Join the two buses into a 6-bits Bus');
gettext('Generic: 6-bits generic constant (0-63)');
gettext('06-Sys-reg-rst: 6 bits system register with reset. Verilog implementation');
gettext('## Example: Manual testing of the 8-to-1 Mux\n\nEight signals with duty cycles of 100%, 50%, 25%, 12%, 6%, 3% and 1.5% are selected and displayed on \nLED7. When the button is pressed, the next channel is selected, starting from channel 0');
gettext('**8-to-1 Mux**');
gettext('### 12%');
gettext('### 6%');
gettext('### 3%');
gettext('### 1.5%');
gettext('05-Mux-8-1-button-LED');
gettext('Reg-x03: 3-bits register');
gettext('DFF-03: Three D flip-flops in paralell');
gettext('DFF-04: Three D flip-flops in paralell');
gettext('DFF-05: five D flip-flops in paralell');
gettext('DFF-rst-x06: Six D flip-flops in paralell with reset');
gettext('DFF-rst-x02: Two D flip-flops in paralell with reset');
gettext('05-Mux-8-1-button-LED');
gettext('05-Mux-8-1-button-LED');
gettext('05-Mux-8-1-button-LED');
Expand Down Expand Up @@ -759,7 +776,9 @@ gettext('iCESugar-1.5');
gettext('12-deMux-1-8-Bus-button-LEDs');
gettext('Display16-8: Display a 16-bits value on an 8-LEDs. The sel input selects the byte to display ');
gettext('2-to-1 Multplexer (8-bit channels)');
gettext('TFF-verilog. System TFF with toggle input: It toogles on every system cycle if the input is active. Verilog implementation');
gettext('## Example: Manual testing of the 2-bits 1-to-8 DeMux\n\nThe constant 0x3 is sent to output channels 0 - 7 depending on the \ncounter. When the button is pressed, the counter is increased and \nthe next LED is turned on');
gettext('Byte 0 \n(least significant) ');
gettext('12-deMux-1-8-Bus-button-LEDs');
gettext('Display16-4: Display a 16-bits value on an 4-LEDs. The sel input selects the byte to display ');
gettext('12-deMux-1-8-Bus-button-LEDs');
Expand Down

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