Block probes for Icestudio => Sigrok integration (with Pulseview GUI)
This blocks provide the ability of debug signals inside your FPGA design without the need of external logic analycer.
Each probe permits analyce a number of signals and triggers it on up or down edge.
The probe inputs are the signal bus, for the moment only 8bits signal bus, that capture at your FPGA clock frequency (soon more capture frequency with PLL configs and more signal bus bits).
As parameter you can input the bit on signal bus that triggers capture and the number of clock cicles of capture (soon more blocks with capture by time )
To capture data and show on pulseview, Icestudio has the iceRok plugin, that permits capture and show results on PulseView.
This is a working progress repository and if you have any feedback, comments at issues tab, are very welcome.
For the moment integration is in inmature state and is only in development branch of Icestudio. Comming soon at nightlybuilds.
Install Pulseview at Sigrok page
On windows you need to put pulseview.exe in your PATH
Add probes as blocks in your design and enjoy!
- Carlos Venegas Arrabé,creator, concepts and development Github page, Twitter
- Juan González,concepts and development Github page, Twitter
- FPGAwars community has developed this project in a voluntary and altruistic way since 02/2017.
Licensed under GPL 2.0 and Creative Commons Attribution-ShareAlike 4.0 International License.
