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Releasing a new stable version

Juan Gonzalez-Gomez edited this page May 12, 2022 · 7 revisions

Introduction

The development of icestudio is done in the develop branch of the repository. The version in development is called WIP (Work in Progress). During the WIP cycle, new features and improvements are added. It is not a stable version, in the sense that sometimes it is broken, until a fix is applied

After sometime, the development is frozen and the release cycle starts. During this cycle no new fetures are introduced, but only fixing critical bugs reported by the community. Once it is stabilized, the stable release is launch and a new WIP cycle begins

Releasing a new stable version

The current fronzen versions are called Release candidates (rc). They are published in the release github page so that all the users can test them and report bugs. A typical release cycle will be wip -> rc1 -> rc2 -> ... -> final stable

Steps to release a new stable version

  1. Merge the develop branch into the master branch
  2. Flag that the version is in the stable cycle: Set the WIP constant to false in the Gruntfile.js
  3. Change the message shown on the version windows in the file: app/views/version.html
  4. Write the new version (Ex. 0.7.0-rc1, 0.7.0-rc2, 0.7.0...) in the following files:
  • package.json
  • package-lock.json
  • app/package.json
  • app/package-lock.json
  1. Generate the executables for all the platforms: Got to Github actions, select Stable Release, click on Run workflow menú, select stable release and click on the Run workflow green button

  1. Spend time testing this new rc version. If there are bugs, fix them and repeat from step 4
  2. If no bugs, generate the final stable version (without the rc letter in the version)
  3. Done!

Getting started

Collections

  • Default: Icestudio Default Collection

Stable

Development

  • IceBoards: blocks and examples for the diferent FPGA boards
  • IceComp: Comparators
  • IceArith: Integer arithmetics
  • IceCounter: Counters
  • IceSignals: 1-bit signal managment
  • IcePLL: PLLs
  • IceLEDOscope: Measuring signals
  • IceLEDs: Displaying on LEDs
  • IceHearts: Timming signal generation
  • IceInputs: 1-bit inputs
  • IceRok: Block probes for Icestudio => Sigrok integration (with Pulseview GUI)
  • IceMachines: Working with Machines (simple state machines with a standar interface)
  • IceSerial: Serial Asynchronous communications
  • IceMem: Working with Memories
  • IceMeasure: Measuring cycles and time in your circuits, very easily
  • IceStack: Working with stacks
  • IceFlash: Read from spi serial flash memories
  • IceBus: Accesing and sharing simple buses
  • IceLCD: Components and controllers for LCDs
  • IceUnary: Working with unary numbers
  • IceCrystal: Drive displays from Open Source FPGAs
  • ice-chips-verilog: IceChips is a library of all common discrete logic devices in Verilog
  • ArithmeticBlocks: FPGA signed and unsigned integer operations, 16, 24 and 32 bits, + - * / sqrt min max compare etc.
  • iceSynth: Audio synthesis
  • icebreaker: Blocks and examples for the icebreaker OpenFPGA board
  • Jedi: blocks of the FPGA Jedi hardware Academy
  • LOVE-FPGA: Hardware elements and examples for the LOVE-FPGA project (Linking Of Virtual Electronics to FPGAs)
  • Stdio: Standard Input-Output in different devices
  • CT11: Ejemplos del cuaderno ténico 11: Señales del sistema y Medición con el LEDOscopio
  • Generic: Icestudio Generic Collection
  • Logic: Icestudio Logic Collection
  • IceInterface: Serial, SPI, I2C... (TODO)

Testbenches

Developers

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