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This repository has been archived by the owner on May 9, 2022. It is now read-only.

v1.1.0

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@Jesus89 Jesus89 released this 28 Feb 15:16
· 18 commits to master since this release

General

  • Refactor scripts
  • Added cells_sim.v to vlib
  • Optimize package size: <30%
  • Fixed win64 cross-compilation: (steveicarus/iverilog#148)
  • Added travis build & deploy

Packages

  • Added windows_x86
  • Added windows_amd64
  • Removed windows
  • Updated linux_x86_64
  • Updated linux_i686
  • Updated linux_armv7l
  • Updated linux_aarch64
  • Updated darwin

Travis FPGAwars/toolchain-iverilog