This project implements a Pulse Position Modulation (PPM) encoder and decoder designed for Visible Light Communication (VLC) systems. The encoder converts serial data to parallel data, encodes it using PPM, and transmits it. The decoder receives the PPM signal, decodes it, and converts it back to parallel data.
This project aims to facilitate real-time data collection in marine environments using VLC technology. The PPM encoder and decoder are essential components in achieving reliable data transmission under varying water conditions.
- PPM Encoder: Converts serial data to parallel data, encodes it using PPM, and transmits it.
- PPM Decoder: Receives the PPM signal, decodes it, and converts it back to parallel data.
- Wavelength Adaptation: Adjusts the LED wavelength to optimize data transmission in different water conditions.
Converts the serial input data to parallel output data.
module shift_register (
input wire clk,
input wire rst,
input wire serial_in,
input wire data_ready_rst,
output reg [7:0] parallel_out,
output reg data_ready
);
Stores the PPM data temporarily for encoding and transmission.
module ppm_memory(
input wire clk,
input wire rst,
input wire [7:0] M_in,
input wire control, //0: read; 1: write
input wire [3:0] address,
output reg [7:0] M_out
);
Encodes the data using PPM and transmits it.
module ppm_encoder_tx(
input wire clk,
input wire rst,
input wire [7:0] in_ppm,
input wire [1:0] order, // 00: null; 01: SOF; 10: data; 11: EOF
input wire [9:0] clk_count_ppm,
input wire [1:0] bit_count_ppm,
output reg Dout
);
Integrates the shift register, PPM memory, and PPM encoder for the complete encoding process.
module ppm_encoder(
input wire clk,
input wire rst,
input wire Din,
output wire Dout
);
Decodes the received PPM signal and converts it back to parallel data.
module ppm_decoder(
input wire clk,
input wire rst,
input wire Din,
output reg [7:0] Dout,
output reg D_en, // data enable
output reg F_en // frame enable
);
- Compile and load the Verilog files into your simulation tool or FPGA development environment.
- Instantiate the
ppm_encoder
andppm_decoder
modules in your top-level design. - Provide the necessary input signals to the
ppm_encoder
and connect theppm_decoder
to the output of theppm_encoder
.
Use your preferred Verilog simulation tool (e.g., ModelSim, XSIM) to simulate the functionality of the PPM encoder and decoder. Ensure to provide test benches that simulate various input conditions to validate the design.
- Verilog 2001: Ensure your environment supports Verilog 2001 syntax and constructs.
- FPGA Development Tool: Tools like Vivado, Quartus, or similar for synthesis and implementation.
This project is licensed under the MIT License - see the LICENSE file for details.