Removing the old -RV32 directory name from parts of the documentation (…

…#1196)
FreeRTOS · Nov 20, 2024 · 874fa7b · 874fa7b
1 parent 7e419c2
commit 874fa7b
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Showing 5 changed files with 9 additions and 9 deletions.
diff --git a/...chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h b/...chip_specific_extensions/Pulpino_Vega_RV32M1RM/freertos_risc_v_chip_specific_extensions.h
@@ -31,7 +31,7 @@
  * common across all currently supported RISC-V chips (implementations of the
  * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
  *
- * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that
  *   is common to all currently supported RISC-V chips.  There is only one
  *   portASM.S file because the same file is built for all RISC-V target chips.
  *
@@ -46,7 +46,7 @@
  * compiler's!) include path.  For example, if the chip in use includes a core
  * local interrupter (CLINT) and does not include any chip specific register
  * extensions then add the path below to the assembler's include path:
- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RV32I_CLINT_no_extensions
  *
  */
 

diff --git a/..._specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h b/..._specific_extensions/RV32I_CLINT_no_extensions/freertos_risc_v_chip_specific_extensions.h
@@ -31,7 +31,7 @@
  * common across all currently supported RISC-V chips (implementations of the
  * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
  *
- * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that
  *   is common to all currently supported RISC-V chips.  There is only one
  *   portASM.S file because the same file is built for all RISC-V target chips.
  *
@@ -46,7 +46,7 @@
  * compiler's!) include path.  For example, if the chip in use includes a core
  * local interrupter (CLINT) and does not include any chip specific register
  * extensions then add the path below to the assembler's include path:
- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RV32I_CLINT_no_extensions
  *
  */
 

diff --git a/portable/GCC/RISC-V/chip_specific_extensions/readme.txt b/portable/GCC/RISC-V/chip_specific_extensions/readme.txt
@@ -3,7 +3,7 @@
  * common across all currently supported RISC-V chips (implementations of the
  * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
  *
- * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that
  *   is common to all currently supported RISC-V chips.  There is only one
  *   portASM.S file because the same file is built for all RISC-V target chips.
  *
@@ -18,6 +18,6 @@
  * compiler's!) include path.  For example, if the chip in use includes a core
  * local interrupter (CLINT) and does not include any chip specific register
  * extensions then add the path below to the assembler's include path:
- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RV32I_CLINT_no_extensions
  *
  */
diff --git a/portable/GCC/RISC-V/portASM.S b/portable/GCC/RISC-V/portASM.S
@@ -32,7 +32,7 @@
  * RISC-V ISA), and code which tailors the port to a specific RISC-V chip:
  *
  * + The code that is common to all RISC-V chips is implemented in
- *   FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S.  There is only one
+ *   FreeRTOS\Source\portable\GCC\RISC-V\portASM.S.  There is only one
  *   portASM.S file because the same file is used no matter which RISC-V chip is
  *   in use.
  *

diff --git a/portable/GCC/RISC-V/readme.txt b/portable/GCC/RISC-V/readme.txt
@@ -3,7 +3,7 @@
  * common across all currently supported RISC-V chips (implementations of the
  * RISC-V ISA), and code that tailors the port to a specific RISC-V chip:
  *
- * + FreeRTOS\Source\portable\GCC\RISC-V-RV32\portASM.S contains the code that
+ * + FreeRTOS\Source\portable\GCC\RISC-V\portASM.S contains the code that
  *   is common to all currently supported RISC-V chips.  There is only one
  *   portASM.S file because the same file is built for all RISC-V target chips.
  *
@@ -18,6 +18,6 @@
  * compiler's!) include path.  For example, if the chip in use includes a core
  * local interrupter (CLINT) and does not include any chip specific register
  * extensions then add the path below to the assembler's include path:
- * FreeRTOS\Source\portable\GCC\RISC-V-RV32\chip_specific_extensions\RV32I_CLINT_no_extensions
+ * FreeRTOS\Source\portable\GCC\RISC-V\chip_specific_extensions\RV32I_CLINT_no_extensions
  *
  */