platform: merge rev_c0 and rev_c123 modules.

This improves readability and allows sharing addon resources between revC platforms.

software/glasgow/platform/all.py

@@ -1,3 +1,2 @@
 from .rev_ab import *
-from .rev_c0 import *
-from .rev_c123 import *
+from .rev_c import *

software/glasgow/platform/rev_c123.py → software/glasgow/platform/rev_c.py

@@ -3,12 +3,10 @@
 from .ice40 import *
 
 
-__all__ = ["GlasgowPlatformRevC123"]
+__all__ = ["GlasgowPlatformRevC0", "GlasgowPlatformRevC123"]
 
 
-# In terms of FPGA I/O, the only change from revC0 to revC1 is the addition of a level shifter
-# on the sync port. There are no changes between revC1, revC2 or revC3.
-class GlasgowPlatformRevC123(GlasgowPlatformICE40):
+class _GlasgowPlatformRevC(GlasgowPlatformICE40):
     device      = "iCE40HX8K"
     package     = "BG121"
     default_clk = "clk_if"
@@ -109,11 +107,6 @@ class GlasgowPlatformRevC123(GlasgowPlatformICE40):
                  Subsignal("oe", Pins("K11", dir="o")),
                  Attrs(IO_STANDARD="SB_LVCMOS33")),
 
-        Resource("port_s", 0,
-                 Subsignal("io", Pins("A11"), Attrs(PULLUP=1)),
-                 Subsignal("oe", Pins("B4", dir="o")),
-                 Attrs(IO_STANDARD="SB_LVCMOS33")),
-
         Resource("aux", 0, Pins("A10"), Attrs(IO_STANDARD="SB_LVCMOS33")),
         Resource("aux", 1, Pins("C9"),  Attrs(IO_STANDARD="SB_LVCMOS33")),
 
@@ -129,6 +122,18 @@ class GlasgowPlatformRevC123(GlasgowPlatformICE40):
     ]
 
 
-if __name__ == "__main__":
-    from amaranth_boards.test.blinky import *
-    GlasgowPlatformRevC1().build(Blinky(), do_program=True)
+class GlasgowPlatformRevC0(_GlasgowPlatformRevC):
+    resources = _GlasgowPlatformRevC.resources + [
+        Resource("port_s", 0,
+                 Subsignal("io", Pins("A11")),
+                 Attrs(IO_STANDARD="SB_LVCMOS33")),
+    ]
+
+
+class GlasgowPlatformRevC123(_GlasgowPlatformRevC):
+    resources = _GlasgowPlatformRevC.resources + [
+        Resource("port_s", 0,
+                 Subsignal("io", Pins("A11"), Attrs(PULLUP=1)),
+                 Subsignal("oe", Pins("B4", dir="o")),
+                 Attrs(IO_STANDARD="SB_LVCMOS33")),
+    ]