FPGA based latency measuring tool for Ethernet networks.
The architecture consists of two designs: a packet generator and a packet re-transmitter. The packet generator sends timestamped packets through an Ethernet interface. The packet re-transmitter detects the packets generated by the generator and transmit them back, which are the used by the generator to calculate the latency.
A serial interface on the packet generator can be used to extract the measurements. An application for interfacing with the serial protocol is provided here
The folder scripts contains TCL scripts for generating Vivado generate a
Vivado project for each of the designs. Use the following command to generate
the projects
vivado -mode batch -source scripts/generate_<design>.tcl