| layout | title | description | categories | thumbnail | year | gmeet |
|---|---|---|---|---|---|---|
post |
8-bit Computer |
Hardware implementation of 8-bit Computer |
diode |
thumbnail.png |
2023 |
The project aims to design an 8 bit computer using hardware components. It also includes deisging the PCB of the same. The computer encompasses various modules like ALU, Clock, Registers, RAM, Program Counter, Control unit etc. Based on SAP-1 architecture, this computer will execute different types of simple instructions namely Load, store, add, subtract, jump, halt etc.
- Understanding basics of computer architecture and organization
- Understanding various types of architectures used to build a computer
- Hands-on experience in building a computer
- Get an experience to design a PCB on EasyEDA
The Simple-As-Possible (SAP)-1 computer is a very basic model of a microprocessor containing the fundamental modules required to build a successful microprocessor. The SAP-1 design contains the basic necessities for a functional microprocessor. Its primary purpose is to develop a basic understanding of how a microprocessor works, interacts with memory and other parts of the system like input and output. The instruction set also is very limited and is simple.
This 8 bit Computer is based on (SAP)-1 architecture. It consists of the Clock Module, ALU, Instruction Register, Program Counter, Register A, Register B, Output Register and Control Unit. The Computer is capable of executing various instructions such as Load, Add, Subtract, Jump, Halt, etc. The instructions are kept track of with the program counter and every time it increments the next instruction starts getting executed. The instruction order is manually set by the user into consecutive memory address locations from address 0 after which the computer will execute them sequentially on its own.
The Clock Module of the Computer synchronises all the operations. Initially the program counter is at 0000 and the first instruction is being executed. Every instruction is executed in at most 5 steps. The first two steps of every instruction is the same, that is, to fetch the instruction from memory to the instruction register and to increment the program counter. The four Most Significant Bits of the instruction in the instruction register is sent to the EEPROM which decodes the instruction and the next 3 steps get executed accordingly. After the program cycle is over the next instruction is fetched and the cycle repeats.
The Project aims on building the computer from scratch using IC chips on a breadboard and on a PCB. Both types of implementation require the same components and the computer is built on logic level with various ICs relying on logic gates, MUX, Flip-Flops, counters, etc. Every module is connected to a common BUS in order to transfer data and instructions. On the breadboard, this is done through connecting bread sticks together and connecting them with each module though wires.
The computer’s clock is used to synchronize all operations. The clock is built using the 555 timer IC. It consists of an astable 555 timer, a monostable 555 timer and a bistable 555 timer. We can output either the oscillating pulse(generated by the astable timer) or the manual pulse(generated by the monostable timer) depending on the select line( that is, the value generated by the bistable timer). If select is 1, then the oscillating pulse is given as the output otherwise the manual pulse is the output.
- Schematic of clock module: https://github.com/IEEE-NITK/8-bit-Computer/blob/main/Clock%20Module/Clock%20Module%20Schematic.png?raw=true
Clock Waveform is shown below
Achieved 49.54% duty cycle, with clock frequency of 758.1 Hz.
The registers in a computer are data storage elements used by the CPU. Registers store small amounts of data that the CPU is processing. It usually holds the operands or the instructions that the CPU is currently processing. The 8 bit computer has 3 registers: register A register B and instruction register (IR). Registers A and B are general purpose registers used to store operands (data) or memory pointers (addresses).
The A and B registers are composed of two 4 bit data registers namely 74LS173 and one 74LS245 octal bus. The two 4 bit data registers are driven by the clock module and each receive 4 data bits. The data can be transferred to the octal bus or just stored in the register based on the control pins 1 and 2 (Oe1 and Oe2, which is zero/grounded in our case). The pins 8 and 9 are load pins which are used to control loading of data from input pins to the register, when the load pin is low it loads data into the register and doesn't load when it is high. The output pins of the register are connected to LED’s to show the data stored in it and also connected to the octal bus. The bus has a direction input pin to control the direction of data flow (high, input to output pin flow in our case) and it has an enable pin which transfers data from register to bus when low and doesn’t transfer when high.
- Schematic of Register A: https://github.com/IEEE-NITK/8-bit-Computer/blob/main/Register%20A/Register%20A%20Schematic.png?raw=true
- Schematic of Register B: https://github.com/IEEE-NITK/8-bit-Computer/blob/main/Register%20B/Register%20B%20Schematic.png?raw=true
The instruction register (IR)is very similar to the A and B registers with few differences in working and usage. The IR stores the address of the instructions in 4 bits. The 4 bits are the last four least significant bits (LSB) of the IR. These bits indicate the instruction to be executed and can be loaded to the bus using the enable pin. The remaining 4 bits which are the most significant bits (MSB) of the IR are sent to the instruction decoder.
- Schematic of Instruction Register: https://github.com/IEEE-NITK/8-bit-Computer/blob/main/Instruction%20Register/Instruction%20Register%20Schematic.png?raw=true
The alu in this 8 bit computer performs basic arithmetic like addition and subtraction on 8 bit binary numbers. To perform this, two 4 bit adders have been used (IC 74LS283). The 1st operand(A0-A7) goes directly to each 4 bit adder (1st 4 bits to the 1st adder and the last 4 bits to the other adder). Since the subtraction is of 2s complement form, each bit of the second operand(B0-B7) is 1st fed into one of the inputs of 8 XOR gates(IC 74LS86), and the second input of the 8 XOR gates is a common subtract enable signal. Whenever this subtract enable signal is off, addition takes place between the 2 operands and whenever this signal is on, subtraction takes place between the 2 operands(1st operand - 2nd operand). The output of the 8 XOR gates is the original number whenever the subtract enable signal is off, and the 1s complement form of the 2nd operand whenever the subtract signal is turned on. And this result is fed into the two 4 bit adders in a similar fashion as the 1st operand.
Since the subtraction is 2s complement, the subtract enable signal is itself fed as the carry in of the 1st adder, and the carry out of the 1st 4 bit adder is sent as the carry input to the 2nd 4 bit adder. Note that the resultant number is also of the 2s complement form.
The resultant number at the output(BUS_0-BUS_7) of the 4 bit adders is sent to the octal bus(74LS245) and is displayed using LEDs at the each output pin of the two 4 bit adders.
- Schematic of ALU module: https://github.com/IEEE-NITK/8-bit-Computer/blob/main/ALU/ALU.png
The program counter uses a 74161 IC, which is a 4 bit synchronous counter IC that also consists of parallel load and count enable. The program counter, by default starts from 0000 and increments every program cycle (not the same as every clock cycle). It generates the memory address of the next instruction to be accessed from the RAM and feeds it into the bus, (A0-A3) using the 74245 IC (octal bus). The enable pin allows the count to be incremented every program cycle. The program counter is also capable of reading a 4 bit memory address from the bus using the load enable coming from the control line. This is important for jumping to certain instructions or looping a set of instructions.
- Schematic of Program Counter module https://github.com/IEEE-NITK/8-bit-Computer/blob/main/Program%20Counter/Program%20Counter%20Schematic.png?raw=true
The RAM module stores instructions along with the required addresses or required data to be operated upon. It consists of 2 submodules: the Memory Address Register(MAR) module and the actual RAM module
This module consists of 2:1 mux (74LS157 IC), 4 bit D register(74LS173), a 4 bit dip switch, and a select toggle switch. The select toggle switch, along with the 2:1 mux is used to toggle between address incoming from the bus or address which can be entered manually using the 4 bit dip switch. The incoming address from the bus(BUS_0 to BUS_3) is stored into the 4 bit D Register. One set of inputs of the mux is given from the 4 bit dip switch, while the other set of inputs is given from the output of the D register. The output of the mux is decided by the select toggle switch, which can be toggled physically. This address output (A0-A3) is sent back to the bus, from where the RAM module takes it and operates on it.
The RAM module consists of two 74189 ICs that can store 4 bits of data and have addresses of 4 bitlength giving a total storage capacity of 8 bytes each. They both are used in parallel to achieve a total of 8 bit RAM. The Address input to the 74189 IC comes from the bus (A0-A3) and the data input to the RAM IC’s may come either from the bus or the dip switches. The Input is selected using a 8 bit parallel MUX, which is constructed from 74157 ICs (parallel select quad 2:1 Mux). The output of the RAM ICs is inverted using 7404 IC (Hex inverter) and given to the 74245 IC (octal bus) to be fed into the bus. The write enable is given from a 2:1 mux that selects manual enable or the enable signal given from the control line.
- Schematic of MAR module: https://github.com/IEEE-NITK/8-bit-Computer/blob/main/Memory%20Unit/MAR%20Schematic.png
- Schematic of RAM module: https://github.com/IEEE-NITK/8-bit-Computer/blob/main/Memory%20Unit/RAM%20Schematic.png
The control unit is the module that directs the operations. It instructs the other modules like registers, ALU, RAM on how to respond to the instructions. The control unit in our 8 bit computer consists of 28C16 16K EEPROM that is programmed to translate the instructions and send the correct control signals for each instruction. Each instruction is split into several steps (T0,T1...,T5) and each step gets executed at rising edge of every clock cycle. The control unit also has counter and 6 LEDs that keep track of the step currently being executed. For every instruction the first three steps are for fetching the instructions from the instruction register. The next 2 to 3 steps are decoding and executing the instructions.
- Schematic of Control Unit module: https://github.com/IEEE-NITK/8-bit-Computer/blob/main/Control%20Unit/Control%20Unit.png
The output register displays the output from the registers in decimal format. The sum register in the ALU passes the data to the A register which then is sent to the output register. The output register consists of EEPROM that can be programmed to convert the binary numbers to single digit decimal numbers. It also has 555 timer , counter and a decoder that cycle through each digit of the decimal output so we see each digit blinking at a time. To see the output without the digits blinking we can increase duty cycle by increasing resistance or decreasing capacitance. By this method we will be able to see the output in decimal.
- Schematic of Output Register module: https://github.com/IEEE-NITK/8-bit-Computer/blob/main/Output%20Register/Output%20register.png
The Bus is a communication system that is used to connect and transfer data between all the computer modules. The bus in the 8 bit computer is built with 8 bus strips that are connected with the modules through 8 parallel wires for each module.
The Computer is able to execute set of instructions and give the desired output without any external assistance. It is able to do all the operations that the SAP-1 Computer is capable of doing such as loading, adding, subtracting, displaying the output, etc.
To conclude with, the 8 bit computer can do basic operations on its own and can execute set of instructions given to it as per the user’s requirements, meeting the requirements of the SAP-1 architecture.
We would like to express special thanks to our mentors Anirudh Singh Solanki and Apurva S for their time, effort and guidance throughout the project.
- Albert P. Malvino and Jerald A. Brown, Digital Computer Electronics.
- eater.net and Ben Eater’s Youtube playlist to build an 8 bit computer
- L. Null, J. Lobur, ”The essentials of computer organization and archi- tecture”, Sudbury, MA, Jones and Barlette Publishesrs, 2003