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Merge pull request #11 from dnltz/WIP/dnltz/i2c-gpio-expander
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Add i2c-gpio-expander
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@KrzysztofHerman
KrzysztofHerman authored Nov 22, 2024
2 parents 20a413e + e22b77e commit 1d0a0ad
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15 changes: 10 additions & 5 deletions .github/workflows/drc.yml
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Expand Up @@ -20,7 +20,7 @@ name: DRC
on:
push:
pull_request:
types: [opened, reopened]
branches: [ main]
workflow_dispatch:
inputs:
files:
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id: manual-files
run: |
files_input="${{ github.event.inputs.files }}"
files_json=$(echo "$files_input" | jq -R -s -c 'split(",") | map(select(length > 0))')
echo $files_json
echo "files=$files_json" >> $GITHUB_OUTPUT
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if [[ $file =~ $FileRe ]]; then
ZipRe="\.zip"
GDSRe="\.gds$"
GDSGZRe="\.gds.gz$"
if [[ $file =~ $ZipRe ]]; then
ZIP_FILE="${{ github.workspace }}/${file}"
# Target directory for unpacking
EXTRACT_DIR="${ZIP_FILE%/*}/Folder$Zips"
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echo "Run DRC for $ZipContentFile";
path=$ZipContentFile;
resultpath=${{ github.workspace }}/drc/Results/${ZipContentFile//[\/.]/_}.lyrdb;
RunDRC ${path} ${resultpath}
done
Zips=$((Zips + 1))
elif [[ $file =~ $GDSRe ]]; then
echo "Run DRC for $file";
path=${{ github.workspace }}/${file};
resultpath=${{ github.workspace }}/drc/Results/${file//[\/.]/_}.lyrdb;
RunDRC ${path} ${resultpath}
RunDRC ${path} ${resultpath}
elif [[ $file =~ $GDSGZRe ]]; then
echo "Run DRC for $file";
path=${{ github.workspace }}/${file};
resultpath=${{ github.workspace }}/drc/Results/${file//[\/.]/_}.lyrdb;
RunDRC ${path} ${resultpath}
fi
fi
done
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674 changes: 674 additions & 0 deletions i2c-gpio-expander/COPYING.GPLv3
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24 changes: 24 additions & 0 deletions i2c-gpio-expander/README.rst
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Open Source I2C Gpio Expander
=============================

This directory contains the design files for an 8-bit I2C GPIO expander, developed using IHP's SG13G2 process. This design is part of the MPW run T576. The expander allows communication via I2C to control 8 GPIO pins, suitable for various interfacing and expansion purposes.

Files Included
##############

* RTL source code
* Layout files
* Documentation (TBD)

More Information
################

For additional details, design rationale, and contributions, please check out the original repository at `i2c-gpio-expander`_.

License
#######

This design is open source and available under the `GPLv3 license`_.

.. _GPLv3 license: COPYING.GPLv3
.. _i2c-gpio-expander: https://github.com/aesc-silicon/i2c-gpio-expander
Binary file added i2c-gpio-expander/design_data/gds/SG13G2Top.gds.gz
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245 changes: 245 additions & 0 deletions i2c-gpio-expander/design_data/logs/1_1_yosys.log
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1. Executing RTLIL frontend.
2. Executing Liberty frontend: ./objects/ihp-sg13g2/SG13G2Top/base/lib/sg13g2_stdcell_typ_1p20V_25C.lib
3. Executing Liberty frontend: ./objects/ihp-sg13g2/SG13G2Top/base/lib/sg13g2_io_typ_1p2V_3p3V_25C.lib
4. Executing Verilog-2005 frontend: /home/daniel/work/aesc/i2c-gpio-expander/tools/OpenROAD-flow-scripts/flow/platforms/ihp-sg13g2/cells_clkgate.v
Using ABC speed script.
Extracting clock period from SDC file: ./results/ihp-sg13g2/SG13G2Top/base/clock_period.txt
Setting clock period to 20000
5. Executing HIERARCHY pass (managing design hierarchy).
5.1. Analyzing design hierarchy..
5.2. Analyzing design hierarchy..
synth -top SG13G2Top -run :fine -flatten -extra-map /home/daniel/work/aesc/i2c-gpio-expander/tools/OpenROAD-flow-scripts/flow/platforms/common/lcu_kogge_stone.v
6. Executing SYNTH pass.
6.1. Executing HIERARCHY pass (managing design hierarchy).
6.1.1. Analyzing design hierarchy..
6.1.2. Analyzing design hierarchy..
6.2. Executing PROC pass (convert processes to netlists).
6.2.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
6.2.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
6.2.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
6.2.4. Executing PROC_INIT pass (extract init attributes).
6.2.5. Executing PROC_ARST pass (detect async resets in processes).
6.2.6. Executing PROC_ROM pass (convert switches to ROMs).
6.2.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
6.2.8. Executing PROC_DLATCH pass (convert process syncs to latches).
6.2.9. Executing PROC_DFF pass (convert process syncs to FFs).
6.2.10. Executing PROC_MEMWR pass (convert process memory writes to cells).
6.2.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
6.2.12. Executing OPT_EXPR pass (perform const folding).
6.3. Executing FLATTEN pass (flatten design).
6.4. Executing OPT_EXPR pass (perform const folding).
6.5. Executing OPT_CLEAN pass (remove unused cells and wires).
6.6. Executing CHECK pass (checking for obvious problems).
6.7. Executing OPT pass (performing simple optimizations).
6.7.1. Executing OPT_EXPR pass (perform const folding).
6.7.2. Executing OPT_MERGE pass (detect identical cells).
6.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
6.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
6.7.5. Executing OPT_MERGE pass (detect identical cells).
6.7.6. Executing OPT_DFF pass (perform DFF optimizations).
6.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
6.7.8. Executing OPT_EXPR pass (perform const folding).
6.7.9. Rerunning OPT passes. (Maybe there is more to do..)
6.7.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
6.7.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
6.7.12. Executing OPT_MERGE pass (detect identical cells).
6.7.13. Executing OPT_DFF pass (perform DFF optimizations).
6.7.14. Executing OPT_CLEAN pass (remove unused cells and wires).
6.7.15. Executing OPT_EXPR pass (perform const folding).
6.7.16. Rerunning OPT passes. (Maybe there is more to do..)
6.7.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
6.7.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
6.7.19. Executing OPT_MERGE pass (detect identical cells).
6.7.20. Executing OPT_DFF pass (perform DFF optimizations).
6.7.21. Executing OPT_CLEAN pass (remove unused cells and wires).
6.7.22. Executing OPT_EXPR pass (perform const folding).
6.7.23. Finished OPT passes. (There is nothing left to do.)
6.8. Executing FSM pass (extract and optimize FSM).
6.8.1. Executing FSM_DETECT pass (finding FSMs in design).
6.8.2. Executing FSM_EXTRACT pass (extracting FSM from design).
6.8.3. Executing FSM_OPT pass (simple optimizations of FSMs).
6.8.4. Executing OPT_CLEAN pass (remove unused cells and wires).
6.8.5. Executing FSM_OPT pass (simple optimizations of FSMs).
6.8.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
6.8.7. Executing FSM_INFO pass (dumping all available information on FSM cells).
6.8.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
6.9. Executing OPT pass (performing simple optimizations).
6.9.1. Executing OPT_EXPR pass (perform const folding).
6.9.2. Executing OPT_MERGE pass (detect identical cells).
6.9.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
6.9.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
6.9.5. Executing OPT_MERGE pass (detect identical cells).
6.9.6. Executing OPT_DFF pass (perform DFF optimizations).
6.9.7. Executing OPT_CLEAN pass (remove unused cells and wires).
6.9.8. Executing OPT_EXPR pass (perform const folding).
6.9.9. Rerunning OPT passes. (Maybe there is more to do..)
6.9.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
6.9.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
6.9.12. Executing OPT_MERGE pass (detect identical cells).
6.9.13. Executing OPT_DFF pass (perform DFF optimizations).
6.9.14. Executing OPT_CLEAN pass (remove unused cells and wires).
6.9.15. Executing OPT_EXPR pass (perform const folding).
6.9.16. Rerunning OPT passes. (Maybe there is more to do..)
6.9.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
6.9.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
6.9.19. Executing OPT_MERGE pass (detect identical cells).
6.9.20. Executing OPT_DFF pass (perform DFF optimizations).
6.9.21. Executing OPT_CLEAN pass (remove unused cells and wires).
6.9.22. Executing OPT_EXPR pass (perform const folding).
6.9.23. Finished OPT passes. (There is nothing left to do.)
6.10. Executing WREDUCE pass (reducing word size of cells).
6.11. Executing PEEPOPT pass (run peephole optimizers).
6.12. Executing OPT_CLEAN pass (remove unused cells and wires).
6.13. Executing ALUMACC pass (create $alu and $macc cells).
6.14. Executing SHARE pass (SAT-based resource sharing).
6.15. Executing OPT pass (performing simple optimizations).
6.15.1. Executing OPT_EXPR pass (perform const folding).
6.15.2. Executing OPT_MERGE pass (detect identical cells).
6.15.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
6.15.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
6.15.5. Executing OPT_MERGE pass (detect identical cells).
6.15.6. Executing OPT_DFF pass (perform DFF optimizations).
6.15.7. Executing OPT_CLEAN pass (remove unused cells and wires).
6.15.8. Executing OPT_EXPR pass (perform const folding).
6.15.9. Rerunning OPT passes. (Maybe there is more to do..)
6.15.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
6.15.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
6.15.12. Executing OPT_MERGE pass (detect identical cells).
6.15.13. Executing OPT_DFF pass (perform DFF optimizations).
6.15.14. Executing OPT_CLEAN pass (remove unused cells and wires).
6.15.15. Executing OPT_EXPR pass (perform const folding).
6.15.16. Finished OPT passes. (There is nothing left to do.)
6.16. Executing MEMORY pass.
6.16.1. Executing OPT_MEM pass (optimize memories).
6.16.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
6.16.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).
6.16.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).
6.16.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
6.16.6. Executing OPT_CLEAN pass (remove unused cells and wires).
6.16.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
6.16.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
6.16.9. Executing OPT_CLEAN pass (remove unused cells and wires).
6.16.10. Executing MEMORY_COLLECT pass (generating $mem cells).
6.17. Executing OPT_CLEAN pass (remove unused cells and wires).
7. Executing SYNTH pass.
7.1. Executing OPT pass (performing simple optimizations).
7.1.1. Executing OPT_EXPR pass (perform const folding).
7.1.2. Executing OPT_MERGE pass (detect identical cells).
7.1.3. Executing OPT_DFF pass (perform DFF optimizations).
7.1.4. Executing OPT_CLEAN pass (remove unused cells and wires).
7.1.5. Rerunning OPT passes. (Removed registers in this run.)
7.1.6. Executing OPT_EXPR pass (perform const folding).
7.1.7. Executing OPT_MERGE pass (detect identical cells).
7.1.8. Executing OPT_DFF pass (perform DFF optimizations).
7.1.9. Executing OPT_CLEAN pass (remove unused cells and wires).
7.1.10. Finished fast OPT passes.
7.2. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
7.3. Executing OPT pass (performing simple optimizations).
7.3.1. Executing OPT_EXPR pass (perform const folding).
7.3.2. Executing OPT_MERGE pass (detect identical cells).
7.3.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
7.3.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
7.3.5. Executing OPT_MERGE pass (detect identical cells).
7.3.6. Executing OPT_SHARE pass.
7.3.7. Executing OPT_DFF pass (perform DFF optimizations).
7.3.8. Executing OPT_CLEAN pass (remove unused cells and wires).
7.3.9. Executing OPT_EXPR pass (perform const folding).
7.3.10. Rerunning OPT passes. (Maybe there is more to do..)
7.3.11. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
7.3.12. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
7.3.13. Executing OPT_MERGE pass (detect identical cells).
7.3.14. Executing OPT_SHARE pass.
7.3.15. Executing OPT_DFF pass (perform DFF optimizations).
7.3.16. Executing OPT_CLEAN pass (remove unused cells and wires).
7.3.17. Executing OPT_EXPR pass (perform const folding).
7.3.18. Rerunning OPT passes. (Maybe there is more to do..)
7.3.19. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
7.3.20. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
7.3.21. Executing OPT_MERGE pass (detect identical cells).
7.3.22. Executing OPT_SHARE pass.
7.3.23. Executing OPT_DFF pass (perform DFF optimizations).
7.3.24. Executing OPT_CLEAN pass (remove unused cells and wires).
7.3.25. Executing OPT_EXPR pass (perform const folding).
7.3.26. Finished OPT passes. (There is nothing left to do.)
7.4. Executing TECHMAP pass (map to technology primitives).
7.4.1. Executing Verilog-2005 frontend: /opt/elements/oss-cad-suite/lib/../share/yosys/techmap.v
7.4.2. Executing Verilog-2005 frontend: /home/daniel/work/aesc/i2c-gpio-expander/tools/OpenROAD-flow-scripts/flow/platforms/common/lcu_kogge_stone.v
7.4.3. Continuing TECHMAP pass.
7.5. Executing OPT pass (performing simple optimizations).
7.5.1. Executing OPT_EXPR pass (perform const folding).
7.5.2. Executing OPT_MERGE pass (detect identical cells).
7.5.3. Executing OPT_DFF pass (perform DFF optimizations).
7.5.4. Executing OPT_CLEAN pass (remove unused cells and wires).
7.5.5. Finished fast OPT passes.
7.6. Executing ABC pass (technology mapping using ABC).
7.6.1. Extracting gate netlist of module `\SG13G2Top' to `<abc-temp-dir>/input.blif'..
7.7. Executing OPT pass (performing simple optimizations).
7.7.1. Executing OPT_EXPR pass (perform const folding).
7.7.2. Executing OPT_MERGE pass (detect identical cells).
7.7.3. Executing OPT_DFF pass (perform DFF optimizations).
7.7.4. Executing OPT_CLEAN pass (remove unused cells and wires).
7.7.5. Finished fast OPT passes.
7.8. Executing HIERARCHY pass (managing design hierarchy).
7.8.1. Analyzing design hierarchy..
7.8.2. Analyzing design hierarchy..
7.9. Printing statistics.
7.10. Executing CHECK pass (checking for obvious problems).
8. Executing OPT pass (performing simple optimizations).
8.1. Executing OPT_EXPR pass (perform const folding).
8.2. Executing OPT_MERGE pass (detect identical cells).
8.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
8.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
8.5. Executing OPT_MERGE pass (detect identical cells).
8.6. Executing OPT_DFF pass (perform DFF optimizations).
8.7. Executing OPT_CLEAN pass (remove unused cells and wires).
8.8. Executing OPT_EXPR pass (perform const folding).
8.9. Rerunning OPT passes. (Maybe there is more to do..)
8.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
8.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
8.12. Executing OPT_MERGE pass (detect identical cells).
8.13. Executing OPT_DFF pass (perform DFF optimizations).
8.14. Executing OPT_CLEAN pass (remove unused cells and wires).
8.15. Executing OPT_EXPR pass (perform const folding).
8.16. Finished OPT passes. (There is nothing left to do.)
9. Executing TECHMAP pass (map to technology primitives).
9.1. Executing Verilog-2005 frontend: /home/daniel/work/aesc/i2c-gpio-expander/tools/OpenROAD-flow-scripts/flow/platforms/ihp-sg13g2/cells_latch.v
9.2. Continuing TECHMAP pass.
10. Executing DFFLIBMAP pass (mapping DFF cells to sequential cells from liberty file).
Warning: Found unsupported expression 'SCE*SCD+SCE'*D' in pin attribute of cell 'sg13g2_sdfbbp_1' - skipping.
10.1. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).
11. Executing OPT pass (performing simple optimizations).
11.1. Executing OPT_EXPR pass (perform const folding).
11.2. Executing OPT_MERGE pass (detect identical cells).
11.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
11.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
11.5. Executing OPT_MERGE pass (detect identical cells).
11.6. Executing OPT_DFF pass (perform DFF optimizations).
11.7. Executing OPT_CLEAN pass (remove unused cells and wires).
11.8. Executing OPT_EXPR pass (perform const folding).
11.9. Rerunning OPT passes. (Maybe there is more to do..)
11.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
11.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
11.12. Executing OPT_MERGE pass (detect identical cells).
11.13. Executing OPT_DFF pass (perform DFF optimizations).
11.14. Executing OPT_CLEAN pass (remove unused cells and wires).
11.15. Executing OPT_EXPR pass (perform const folding).
11.16. Finished OPT passes. (There is nothing left to do.)
abc -script /home/daniel/work/aesc/i2c-gpio-expander/tools/OpenROAD-flow-scripts/flow/scripts/abc_speed.script -liberty ./objects/ihp-sg13g2/SG13G2Top/base/lib/sg13g2_stdcell_typ_1p20V_25C.lib -constr ./objects/ihp-sg13g2/SG13G2Top/base/abc.constr -dont_use sg13g2_lgcp_1 -dont_use sg13g2_sighold -dont_use sg13g2_slgcp_1 -dont_use sg13g2_dfrbp_2 -D 20000
12. Executing ABC pass (technology mapping using ABC).
12.1. Extracting gate netlist of module `\SG13G2Top' to `<abc-temp-dir>/input.blif'..
12.1.1. Executing ABC.
12.1.2. Re-integrating ABC results.
13. Executing SETUNDEF pass (replace undef values with defined constants).
14. Executing SPLITNETS pass (splitting up multi-bit signals).
15. Executing OPT_CLEAN pass (remove unused cells and wires).
16. Executing HILOMAP pass (mapping to constant drivers).
17. Executing INSBUF pass (insert buffer cells for connected wires).
18. Executing CHECK pass (checking for obvious problems).
19. Printing statistics.
20. Executing Verilog backend.
exec cp /home/daniel/work/aesc/i2c-gpio-expander/modules/elements/zibal//build//I2cGpioExpander/SG13G2/zibal/SG13G2Top.sdc ./results/ihp-sg13g2/SG13G2Top/base/1_synth.sdc
Warnings: 1 unique messages, 9 total
End of script. Logfile hash: c84b56985f, CPU: user 0.47s system 0.02s, MEM: 28.48 MB peak
Yosys 0.43+11 (git sha1 49f547782, clang++ 14.0.0-1ubuntu1.1 -fPIC -Os)
Time spent: 63% 2x abc (0 sec), 8% 30x opt_clean (0 sec), ...
Elapsed time: 0:01.34[h:]min:sec. CPU time: user 1.27 sys 0.04 (97%). Peak memory: 29160KB.
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