Added fillers and docs for the amux, AIaccelerator doc still missing

CHIPCHILE_CANELOS24_WorkshopTO/doc/source/Integration.rst

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+Top level integration
+======================

CHIPCHILE_CANELOS24_WorkshopTO/doc/source/OpenROAD-flow-scripts.rst

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+OpenROAD-flow-scripts
+======================
+
+Installation
+------------
+The procedure of installation of ORFS is described in the official documentatoion of ORFS as well as
+documented in  the IHP-Open-PDK read the doce webpage. 
+
+Usage
+------
+The orginal ORFS tool provides some example designs, which can be elaborated resulting in core area of the chip. 
+In order to provide full chip design one have to incorporate a padring, which instantiates a specific number of IO 
+cells according to the design specification. 
+
+
+Abstracting analog macro
+------------------------
+ORFS supports macro instantiation, what enables the user to encapsulate the design and instatiate it at a top level as a
+separate block. In order to do so one have to deliver certain views of the macro and inform ORFS about the macro location. 
+The views are the following: ``verilog``, ``liberty``, ``lef``, ``gds``. 
+
+In order to instantiate an analog macro a 

CHIPCHILE_CANELOS24_WorkshopTO/doc/source/analogiface.rst

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+Analog Interface
+-------------------
+
+The analog part cosist of eight trasmission gates isolated by a dedicated guard ring,
+what should improve isolation between channes. The basic schematic of a trasmission gate 
+is shown below
+
+.. image:: _static/multiplexer_cir.png
+  :width: 400
+  :alt: Alternative text
+
+
+A complete module of the multiplexer is presented on the following figure, where a symbol for a basic 
+module of the gate and symbol for multiplexer were used in order to abstract the circuit.
+
+.. image:: _static/multiplexer.png
+  :width: 800
+  :alt: Alternative text
+
+
+Design Steps
+-------------
+
+The principal parameter o the analog switch is it's on-state resistance, which limits the maximum current of the device. 
+Assuming the maximum voltage drop of :math:`\Delta V` @ :math:`I_{max}` load current one can calculate the respective resistance
+using simple Ohms law :math:`R_{ON} = \frac{\Delta V}{I_{max}}`
+
+.. image:: _static/an_switch.jpg
+  :width: 600
+  :alt: Alternative text
+
+In our case the maximum input voltage is 1.2 V so assuming 10% of the voltage drop @ maximum current of 10 mA we can derive 12 Ohm 
+on state resistance. See te following figure:
+
+
+.. image:: _static/iload_pos.png
+  :width: 600
+  :alt: Alternative text
+
+
+For the MOSFET transistor the static  channel resistance can be calculated as  :math:`R_{DSON} = \frac{V_{DS}}{I_{DS}}`.
+So in order to calculate the transistor size we have to calculete the device current, in this case :math:`I_{DS} = \frac{V_{DS}}{R_{ON}}`
+:math:`I_{DS} = \frac{1.2}{12} = 0.1 mA`.  One single device of a unit width of 1 um  and length of 0.13 um can handle approx 400 uA of current so in order to get 
+the 100 mA we have to increase th width 250 times. Since the allowed value of a unit finger width is 10 um we have to create  multifinger device by applying ng=25. 
+
+
+Sweeping the load curent form 10u to 100 mA one can get the value of the on state resistance shown below:
+
+
+.. image:: _static/iload_ron.png
+  :width: 600
+  :alt: Alternative text
+
+
+
+
+

CHIPCHILE_CANELOS24_WorkshopTO/doc/source/architecture.rst

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+Architecture of the analog multiplexer chip
+===========================================
+
+The chip level architecture of the multiiplexer is shown on the figure below
+
+.. image:: _static/chip_arch.png
+  :width: 800
+  :alt: Alternative text
+
+The circuit consist of eight analog switches (transmission gates), digital interface based on SPI bus
+and respective IO cells. The detailed description of the building blocks will be presented in the following 
+subsections.
+
+.. toctree::
+
+   analogiface
+   digitaliface
+

CHIPCHILE_CANELOS24_WorkshopTO/doc/source/conf.py

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 # -- Project information
 
-project = 'Amazing Design'
-copyright = '2024, IHP Open PDK'
-author = 'Amazing Design Authors'
+project = 'CanelosWorkshop'
+copyright = '2024, Canelos'
+author = 'Graziella'
 
 release = '0.1'
 version = '0.1.0'

CHIPCHILE_CANELOS24_WorkshopTO/doc/source/digitaliface.rst

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+Digital Interface
+-------------------
+
+The digital interface is based on a basic version of a SPI (Serial Peripherial Interface) bus.
+The verilog module deinition establishes the interface signals. Apart standard signaling 
+like ``clk, mosi, miso, ss`` the module is clocked by general ``clock`` signal and have 
+parell input/output data access via ``dion/dout`` buses. Once the transmission of 8 bits is completed
+a ``done`` signal is asserted by the module. 
+
+.. code-block:: verilog
+
+  module spi(
+      input clk,
+      input rst,
+      input ss,
+      input mosi,
+      output miso,
+      input sck,
+      output done,
+      input [7:0] din,
+      output [7:0] dout
+    );
+   
+Since the design of analog multiplexer require digital control signals the presented design we will
+not use input paralell interface. Instead the SPI module was wrapped by a module named ``control``
+in order to expose only the necesary signals and enable compementary signal generation (every transmission
+gate need a pair of control signals). 
+

CHIPCHILE_CANELOS24_WorkshopTO/doc/source/index.rst

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+Welcome to Mixed Signal design track documentation!
+======================================================
 
-********************************************************
-Welcome to Amazing Design Open Source PDK documentation!
-********************************************************
 
+.. note::
 
-.. toctree::
-    :hidden:
-
-    specification
-    designdata
-    validation
+   This documentation is to help the participants of Canelos Workshop to 
+   design an analog/switch multiplexer using open source tools and IHP-Open=PDK.
 
-.. warning::
-    This documentation is currently a **work in progress**.
+Contents
+--------
 
-.. image:: _static/IHP_logo.png
-    :align: center
-    :alt: IHP Logo Image.
-    :width: 400
+.. toctree::
 
+   schedule
+   resources
+   spec
+   architecture
+   schematic
+   simulation
+   testbenches
+   layout
+   physicalverification
+   OpenROAD-flow-scripts
+   Integration

CHIPCHILE_CANELOS24_WorkshopTO/doc/source/layout.rst

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+Layout design using Klayout
+=============================
+
+In this workshop, we will explore the fundamentals of layout design for mixed-signal microelectronics using KLayout, an open-source layout editor. Utilizing the IHP SG13G2 PDK, we will ensure our designs meet the necessary fabrication requirements, guiding you through the essential steps to create and verify layouts for manufacturing.
+
+Parametric Cells
+----------------
+
+PCells, or Parameterized Cells, are reusable layout components that can be customized by adjusting parameters such as width, length, or device type. This allows designers to efficiently create and modify layout elements without redrawing them from scratch.
+
+Instantiating PCells in KLayout:
+
+1. Open KLayout in edit mode using:
+
+.. code-block:: bash
+    
+    klayout -e
+
+2. Change the technology from 'Default' to 'sg13g2':
+
+.. image:: _static/klayout_tech.png
+  :width: 600
+  :alt: Alternative text
+
+3. Now you need to create a new layout. To do this, go to the File tab and select New Layout. Make sure to choose the correct technology by verifying that it is IHP SG13G2, and then click OK to proceed. 
+
+.. image:: _static/klayout_new.png
+  :width: 600
+  :alt: Alternative text
+
+4. The next step is to select the PCell library from the window at the bottom left. A list of all available PCells will appear.
+
+.. image:: _static/klayout_lib.png
+  :width: 600
+  :alt: Alternative text
+
+5. To instantiate a PCell, simply select the desired PCell and drag it into the workspace. Once instantiated, you can modify its parameters by double-clicking on the PCell.
+
+.. image:: _static/klayout_pcell.png
+  :width: 600
+  :alt: Alternative text
+
+
+Design Rule Checks
+------------------
+
+Design Rule Checks (DRC) are essential in ensuring that your layout complies with the manufacturing rules of the foundry. These rules define the minimum spacing, width, and other geometrical constraints that must be followed to ensure a successful fabrication.
+
+1. To run the DRC check, go to the Tools tab, select DRC, and then choose the Minimal or Maximal Verification file.
+
+.. image:: _static/klayout_drc.png
+  :width: 600
+  :alt: Alternative text
+
+2. To view the DRC results, go to the Tools tab and select Marker Browser. In the pop-up window, choose the corresponding database.
+
+.. image:: _static/klayout_drc_check.png
+  :width: 600
+  :alt: Alternative text
+
+
+Layout vs. Schematic
+--------------------
+
+LVS (Layout vs. Schematic) is a verification step that ensures your layout matches the schematic at a netlist level. This step is crucial in confirming that the physical layout correctly represents the intended design functionality.
+
+1. First, you need to correctly extract the netlist from Xschem. To do this, open your schematic in Xschem, go to the Simulation menu, select LVS, then choose the LVS Netlist option, and make sure to uncheck the Use SpicePrefix option.
+
+.. image:: _static/xschem_lvs.png
+  :width: 600
+  :alt: Alternative text
+
+2. Now, navigate to the SG13G2 PDK tab and click on SG13G2 LVS Options. In the pop-up window, enter the path of the netlist file that you want to use for the LVS check.
+
+.. image:: _static/klayout_lvs_conf.png
+  :width: 600
+  :alt: Alternative text
+
+3. Finally, in the same SG13G2 PDK tab, select Run KLayout LVS. The LVS process will begin, and a window displaying the results will appear once it’s complete.
+
+.. image:: _static/klayout_lvs_final.png
+  :width: 600
+  :alt: Alternative text

CHIPCHILE_CANELOS24_WorkshopTO/doc/source/physicalverification.rst

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+Physical Verification
+=======================
+
+
+Design Rule Check
+------------------
+
+
+Layout Versus Schematic
+-------------------------
+
+
+

CHIPCHILE_CANELOS24_WorkshopTO/doc/source/resources.rst

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+Resources
+==========
+
+The PDK documentation can be found `here <https://ihp-open-pdk-docu.readthedocs.io/en/latest/workflow.html>`_.
+
+The tools/docker image can be found `here <>`_. 
+
+
+Datasheets of some analog multiplexers/switches
+------------------------------------------------
+
+Analog multiplexer form AD  :download:`ADG1634l <_static/adg1634l.pdf>`
+
+Analog multiplexer form MAXIM  :download:`MAX14778 <_static/MAX14778.pdf>`
+

CHIPCHILE_CANELOS24_WorkshopTO/doc/source/schedule.rst

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+Schedule
+==========
+
+
+Day 1 - Intrduction
+----------------------------------------------
+#. General information about mixed signal design
+#. Review of some analog multiplexers.
+#. Review of building blocks.
+#. Review of tools, PDK and flow to be used. 
+
+Day 2 - Analog, Digital and mixed mode simulations
+--------------------------------------------------------
+
+#. Digital modeling of a SPI interface IP + testbench. 
+#. Analog modeling of an analog multiplexer. 
+#. A simple example of a mixed mode simulation using xschem, ngspice and verilator. 
+#. Extension of a basic example of mixed mode simulation to support SPI blocks
+#. Top level simulation of the circuit using analog multiplexer, SPI module and IO modules. 
+#. Running testbenches to evaluate the circuit performance. 
+
+Day 3 - Physical design
+---------------------------
+
+#. Floorplaning
+#. Digital block synthesis
+#. Analog mux layout
+#. Physical checks DRC + LVS
+#. Macros instantiation + top level routng
+#. Top level physical checks. 
+
+

CHIPCHILE_CANELOS24_WorkshopTO/doc/source/schematic.rst

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+Schematic capture
+==================
+
+
+.. image:: _static/spitest_sch.png
+  :width: 800
+  :alt: Alternative text
+
+
+The cruitial part of the schematic is the symbol of the digital module  which shoulf ``pin to pin`` compatible with the verilog module.
+It is important to ensure the correct order of the input/output pins. The buses are not supported so it should de expanded to a binary signals in the 
+spice netlist as shown below:
+
+Verilog module defintion:
+
+.. code-block:: verilog
+
+  module control(
+    input clk,
+    input rst,
+    input sck,
+    input mosi,
+    input ss,
+    output miso,
+    output [7:0] dout
+  );
+
+
+Xschem symbol defintion ``*.sym``:
+
+
+.. code-block:: bash
+
+   format="@name [ @@clk @@rst @@sck @@mosi @@ss ] [ @@miso @@dout_0 @@dout_1 @@dout_2 @@dout_3 @@dout_4 @@dout_5 @@dout_6 @@dout_7  ] null @dut 
+
+The graphical representation of the symbol is shown below
+
+.. image:: _static/spitest_sym.png
+  :width: 400
+  :alt: Alternative text