KTU MLAB first tape out: Transconductance amplifier

[Tomuks123159]

No description provided.

[Tomuks123159]

DiffAmp_NOFILL.gds ran into DRC errors, but another gds DiffAmp.gds is errors free. Should I delete the failed one or leave it as it is?

[Tomuks123159]

Fixed

[KrzysztofHerman]

@Tomuks123159 thank you for submission.

After the initial review please fix the following:

1. Provide specification and documentation in doc/ directory. Document results of your simulations and the design process.
2. Use adequate directory structure under design_data/ directory.
3. Provide test benches for your circuit, which proof that your design meet the specification.
4. Provide LVS and DRC reports which proof that your design has no serious issues related to the physical design.
5. Update the PDK to the latest main branch and replace the seal ring with the one from the latest PDK.
6. Remove all fillers and fill again using filler scripts.

[Tomuks123159]

Why does the DRC show metal density errors even after running the fill scripts?

[KrzysztofHerman]

Could you post the DRC log and a screenshot with the DRCs on the layout please ?

[Tomuks123159]

log.txt

[KrzysztofHerman]

Have you run Density report ? Maybe you are already outside the upper limit of the global densities.
Anyway in the script sg13g2_filler_Metal.lym you can change the size and distance between the fillers and thus modify the density.
Be careful fith the DRC rules for fillers (page 37 of layout manual)

[KrzysztofHerman]

@Tomuks123159
Your design is DRC clean,
I have checked out also the xchem files and you should have consistent names between ota.sym and the actual subcircuit ie. ota.sch. Moreover the simulation you provide does calculate something but still we are lacking the specification and more documentation.
Please provide some more design goals along with: Vdd 3.3V and GBW 4 MHz

[Tomuks123159]

@KrzysztofHerman
I would like to ask: when is the deadline for the submission? In the IHP-Open-DesignLib documentation, it states: "The time window for evaluation & selection will be around 10 days (it may differ between different shuttles)."

We are still working on the documentation (we have successfully created test benches, and you can find screenshots of the results in the pictures folder). Is it too late to make changes? Or can we complete the documentation formatting after submission?

P.S. .rst is new to us, and we are still trying to get the hang of it.

[KrzysztofHerman]

The deadline for submitting changes is today 21/11/2024 23:59 CET time. You can submit the documentation later as a separate PR.

[KrzysztofHerman]

I have reviewed a little bit the documentation and you could do the following:

1. Review this NGSPICE code

set hcopydevtype=svg
set color0=white
set color1=black
set color2=red
set color3=blue
set color4=green
hardcopy Bandwidth.svg s_2_1  title 'Transfer function' xlabel 'frequency' ylabel 'S_21' xlog

It was taken from here. This way you can stream the formatted images to a vector/rasater high quality graphics.

2. Review this NGSPICE example:

** sch_path: /home/herman/github/KrzysztofHerman/IHP-Open-PDK/ihp-sg13g2/libs.tech/xschem/sg13g2_tests_xyce/tran_logic_nand.sch
**.subckt tran_logic_nand
VinA A GND dc 0 ac 0 pulse(0 1.2 2n 100p 100p 4n 6n )
Vdd net1 GND 1.2
XM1 net2 A GND GND sg13_lv_nmos w=1.0u l=0.45u ng=1 m=1
XM2 out A net1 net1 sg13_lv_pmos w=1.0u l=0.45u ng=1 m=1
XM3 out B net1 net1 sg13_lv_pmos w=1.0u l=0.45u ng=1 m=1
XM4 out B net2 GND sg13_lv_nmos w=1.0u l=0.45u ng=1 m=1
VinB B GND dc 0 ac 0 pulse(0 1.2 0 100p 100p 2n 4n )
**** begin user architecture code

.lib cornerMOSlv.lib mos_tt
.param temp=27
.control
tran 50p 20n
meas tran tdelay TRIG v(a) VAl=0.9 FALl=1 TARG v(out) VAl=0.9 RISE=1

echo "+------------+------------+" >> file.rst
echo "|Col1        |   Col2     |" >> file.rst
echo "+============+============+" >> file.rst
echo  |The value of delay is:   | $&tdelay  | >> file.rst
echo "+------------+------------+" >> file.rst
echo "|param       |   value    |" >> file.rst
echo "+------------+------------+" >> file.rst

write tran_logic_nand.raw
.endc

**** end user architecture code
**.ends
.GLOBAL GND
.end

This way you can stream a numeric values out from ngspice and you can even format it as RST.

[KrzysztofHerman]

@Tomuks123159

Congratulations !
You design was accepted for production.
Testfield: T576
Top cell name: DiffAmp_NOFILL