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ports/psoc6: I2S test modify.
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Signed-off-by: IFX-Anusha <Anusha.TR@infineon.com>
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IFX-Anusha committed Oct 23, 2024
1 parent bdf61fd commit 9c79fad
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Showing 5 changed files with 14 additions and 68 deletions.
62 changes: 0 additions & 62 deletions ports/psoc6/machine_i2s.c
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Original file line number Diff line number Diff line change
Expand Up @@ -104,50 +104,6 @@ static int8_t get_frame_mapping_index(int8_t bits, format_t format) {
}
}

// void i2s_audio_clock_init(uint32_t audio_clock_freq_hz) {
// cyhal_clock_t clock_pll;
// cy_rslt_t result;

// static bool clock_set = false;

// result = cyhal_clock_reserve(&clock_pll, &CYHAL_CLOCK_PLL[0]);
// i2s_assert_raise_val("PLL clock reserve failed with error code: %lx", result);

// uint32_t pll_source_clock_freq_hz = cyhal_clock_get_frequency(&clock_pll);

// if (audio_clock_freq_hz != pll_source_clock_freq_hz) {
// mp_printf(&mp_plat_print, "machine.I2S: PLL0 freq is changed from %lu to %lu. This will affect all resources clock freq sourced by PLL0.\n", pll_source_clock_freq_hz, audio_clock_freq_hz);
// clock_set = false;
// pll_source_clock_freq_hz = audio_clock_freq_hz;
// }

// if (!clock_set) {
// result = cyhal_clock_set_frequency(&clock_pll, pll_source_clock_freq_hz, NULL);
// i2s_assert_raise_val("Set PLL clock frequency failed with error code: %lx", result);
// if (!cyhal_clock_is_enabled(&clock_pll)) {
// result = cyhal_clock_set_enabled(&clock_pll, true, true);
// i2s_assert_raise_val("PLL clock enable failed with error code: %lx", result);
// }

// result = cyhal_clock_reserve(&audio_clock, &CYHAL_CLOCK_HF[1]);
// i2s_assert_raise_val("HF1 clock reserve failed with error code: %lx", result);
// result = cyhal_clock_set_source(&audio_clock, &clock_pll);
// i2s_assert_raise_val("HF1 clock sourcing failed with error code: %lx", result);
// result = cyhal_clock_set_divider(&audio_clock, 2);
// i2s_assert_raise_val("HF1 clock set divider failed with error code: %lx", result);
// if (!cyhal_clock_is_enabled(&audio_clock)) {
// result = cyhal_clock_set_enabled(&audio_clock, true, true);
// i2s_assert_raise_val("HF1 clock enable failed with error code: %lx", result);
// }
// cyhal_clock_free(&audio_clock);

// clock_set = true;
// }

// cyhal_clock_free(&clock_pll);

// cyhal_system_delay_ms(1);
// }

static inline bool i2s_dma_is_tx_complete(cyhal_i2s_event_t event) {
return 0u != (event & CYHAL_I2S_ASYNC_TX_COMPLETE);
Expand Down Expand Up @@ -367,21 +323,6 @@ static void mp_machine_i2s_init_helper(machine_i2s_obj_t *self, mp_arg_val_t *ar
mp_raise_ValueError(MP_ERROR_TEXT("invalid format"));
}

// // is valid clock freq?
// uint32_t audio_clock_freq_hz;
// uint32_t rate = args[ARG_rate].u_int;
// if (rate == 8000 ||
// rate == 16000 ||
// rate == 32000 ||
// rate == 48000) {
// audio_clock_freq_hz = AUDIO_SYS_CLOCK_98_304_000_HZ;
// } else if (rate == 22050 ||
// rate == 44100) {
// audio_clock_freq_hz = AUDIO_SYS_CLOCK_90_300_000_HZ;
// } else {
// mp_raise_ValueError(MP_ERROR_TEXT("rate not supported"));
// }

// is valid buf size ?
int32_t ring_buffer_len = args[ARG_ibuf].u_int;
if (ring_buffer_len < 0) {
Expand All @@ -402,9 +343,6 @@ static void mp_machine_i2s_init_helper(machine_i2s_obj_t *self, mp_arg_val_t *ar
self->ring_buffer_storage = m_new(uint8_t, ring_buffer_len);

ringbuf_init(&self->ring_buffer, self->ring_buffer_storage, ring_buffer_len);
// i2s_audio_clock_init(audio_clock_freq_hz);
// audio_i2s_set_frequency(audio_clock_freq_hz, &audio_clock);
// mp_printf(&mp_plat_print, "clock pointer: %p\n", audio_clock);
i2s_init(self, &audio_clock);
i2s_dma_init(self);
}
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3 changes: 1 addition & 2 deletions ports/psoc6/modmachine.c
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Original file line number Diff line number Diff line change
Expand Up @@ -437,9 +437,8 @@ void audio_i2s_set_frequency(uint32_t freq) {
clock_assert_raise_val("PLL clock reserve failed with error code: %lx", result);

uint32_t pll_source_clock_freq_hz = cyhal_clock_get_frequency(&clock_pll);

if (freq != pll_source_clock_freq_hz) {
// mp_printf(&mp_plat_print, "machine.I2S: PLL0 freq is changed from %lu to %lu. This will affect all resources clock freq sourced by PLL0.\n", pll_source_clock_freq_hz, freq);
mp_printf(&mp_plat_print, "machine.I2S: PLL0 freq is changed from %lu to %lu. This will affect all resources clock freq sourced by PLL0.\n", pll_source_clock_freq_hz, freq);
clock_set_i2s = false;
pll_source_clock_freq_hz = freq;
}
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4 changes: 2 additions & 2 deletions tests/ports/psoc6/board_ext_hw/multi/i2s_rx.py
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Original file line number Diff line number Diff line change
Expand Up @@ -112,9 +112,9 @@ def print_i2s_format(raw_buf, bits):
for _bits in test_bits:
for _rate in test_rates:
if _rate == 22050 or _rate == 44100:
freq = 98000000
else:
freq = 90000000
else:
freq = 98000000
machine.freq(freq, machine.AUDIO_I2S)
audio_in = I2S(
0,
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9 changes: 9 additions & 0 deletions tests/ports/psoc6/board_ext_hw/multi/i2s_rx.py.exp
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Original file line number Diff line number Diff line change
@@ -1,30 +1,39 @@
1. tx-rx data for all formats, rates and bit resolution
machine.I2S: PLL0 freq is changed from 48000000 to 98000000. This will affect all resources clock freq sourced by PLL0.
data received for format = 0, bits = 16, rate = 8000 : True
data received for format = 0, bits = 16, rate = 16000 : True
data received for format = 0, bits = 16, rate = 32000 : True
data received for format = 0, bits = 16, rate = 48000 : True
machine.I2S: PLL0 freq is changed from 98000000 to 90000000. This will affect all resources clock freq sourced by PLL0.
data received for format = 0, bits = 16, rate = 22050 : True
data received for format = 0, bits = 16, rate = 44100 : True
machine.I2S: PLL0 freq is changed from 90000000 to 98000000. This will affect all resources clock freq sourced by PLL0.
data received for format = 0, bits = 32, rate = 8000 : True
data received for format = 0, bits = 32, rate = 16000 : True
data received for format = 0, bits = 32, rate = 32000 : True
data received for format = 0, bits = 32, rate = 48000 : True
machine.I2S: PLL0 freq is changed from 98000000 to 90000000. This will affect all resources clock freq sourced by PLL0.
data received for format = 0, bits = 32, rate = 22050 : True
data received for format = 0, bits = 32, rate = 44100 : True
machine.I2S: PLL0 freq is changed from 90000000 to 98000000. This will affect all resources clock freq sourced by PLL0.
data received for format = 1, bits = 16, rate = 8000 : True
data received for format = 1, bits = 16, rate = 16000 : True
data received for format = 1, bits = 16, rate = 32000 : True
data received for format = 1, bits = 16, rate = 48000 : True
machine.I2S: PLL0 freq is changed from 98000000 to 90000000. This will affect all resources clock freq sourced by PLL0.
data received for format = 1, bits = 16, rate = 22050 : True
data received for format = 1, bits = 16, rate = 44100 : True
machine.I2S: PLL0 freq is changed from 90000000 to 98000000. This will affect all resources clock freq sourced by PLL0.
data received for format = 1, bits = 32, rate = 8000 : True
data received for format = 1, bits = 32, rate = 16000 : True
data received for format = 1, bits = 32, rate = 32000 : True
data received for format = 1, bits = 32, rate = 48000 : True
machine.I2S: PLL0 freq is changed from 98000000 to 90000000. This will affect all resources clock freq sourced by PLL0.
data received for format = 1, bits = 32, rate = 22050 : True
data received for format = 1, bits = 32, rate = 44100 : True

2. irq non-blocking read implementation
machine.I2S: PLL0 freq is changed from 90000000 to 98000000. This will affect all resources clock freq sourced by PLL0.
rx blocking done

3. shift
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4 changes: 2 additions & 2 deletions tests/ports/psoc6/board_ext_hw/multi/i2s_tx.py
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Original file line number Diff line number Diff line change
Expand Up @@ -122,9 +122,9 @@ def print_i2s_format(raw_buf, bits):
for _bits in test_bits:
for _rate in test_rates:
if _rate == 22050 or _rate == 44100:
freq = 98000000
else:
freq = 90000000
else:
freq = 98000000
machine.freq(freq, machine.AUDIO_I2S)
audio_out = I2S(
0,
Expand Down

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