ports/psoc6: I2S test modify.

Signed-off-by: IFX-Anusha <Anusha.TR@infineon.com>

ports/psoc6/modmachine.c

@@ -439,7 +439,7 @@ void audio_i2s_set_frequency(uint32_t freq) {
     uint32_t pll_source_clock_freq_hz = cyhal_clock_get_frequency(&clock_pll);
 
     if (freq != pll_source_clock_freq_hz) {
-        mp_printf(&mp_plat_print, "machine.I2S: PLL0 freq is changed from %lu to %lu. This will affect all resources clock freq sourced by PLL0.\n", pll_source_clock_freq_hz, freq);
+        // mp_printf(&mp_plat_print, "machine.I2S: PLL0 freq is changed from %lu to %lu. This will affect all resources clock freq sourced by PLL0.\n", pll_source_clock_freq_hz, freq);
         clock_set_i2s = false;
         pll_source_clock_freq_hz = freq;
     }

tests/ports/psoc6/board_ext_hw/multi/i2s_rx.py.exp

@@ -1,39 +1,30 @@
 1. tx-rx data for all formats, rates and bit resolution
-machine.I2S: PLL0 freq is changed from 48000000 to 98000000. This will affect all resources clock freq sourced by PLL0.
 data received for format = 0, bits = 16, rate = 8000 : True
 data received for format = 0, bits = 16, rate = 16000 : True
 data received for format = 0, bits = 16, rate = 32000 : True
 data received for format = 0, bits = 16, rate = 48000 : True
-machine.I2S: PLL0 freq is changed from 98000000 to 90000000. This will affect all resources clock freq sourced by PLL0.
 data received for format = 0, bits = 16, rate = 22050 : True
 data received for format = 0, bits = 16, rate = 44100 : True
-machine.I2S: PLL0 freq is changed from 90000000 to 98000000. This will affect all resources clock freq sourced by PLL0.
 data received for format = 0, bits = 32, rate = 8000 : True
 data received for format = 0, bits = 32, rate = 16000 : True
 data received for format = 0, bits = 32, rate = 32000 : True
 data received for format = 0, bits = 32, rate = 48000 : True
-machine.I2S: PLL0 freq is changed from 98000000 to 90000000. This will affect all resources clock freq sourced by PLL0.
 data received for format = 0, bits = 32, rate = 22050 : True
 data received for format = 0, bits = 32, rate = 44100 : True
-machine.I2S: PLL0 freq is changed from 90000000 to 98000000. This will affect all resources clock freq sourced by PLL0.
 data received for format = 1, bits = 16, rate = 8000 : True
 data received for format = 1, bits = 16, rate = 16000 : True
 data received for format = 1, bits = 16, rate = 32000 : True
 data received for format = 1, bits = 16, rate = 48000 : True
-machine.I2S: PLL0 freq is changed from 98000000 to 90000000. This will affect all resources clock freq sourced by PLL0.
 data received for format = 1, bits = 16, rate = 22050 : True
 data received for format = 1, bits = 16, rate = 44100 : True
-machine.I2S: PLL0 freq is changed from 90000000 to 98000000. This will affect all resources clock freq sourced by PLL0.
 data received for format = 1, bits = 32, rate = 8000 : True
 data received for format = 1, bits = 32, rate = 16000 : True
 data received for format = 1, bits = 32, rate = 32000 : True
 data received for format = 1, bits = 32, rate = 48000 : True
-machine.I2S: PLL0 freq is changed from 98000000 to 90000000. This will affect all resources clock freq sourced by PLL0.
 data received for format = 1, bits = 32, rate = 22050 : True
 data received for format = 1, bits = 32, rate = 44100 : True
 
 2. irq non-blocking read implementation 
-machine.I2S: PLL0 freq is changed from 90000000 to 98000000. This will affect all resources clock freq sourced by PLL0.
 rx blocking done
 
 3. shift