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ports/psoc6/machine_i2s.c: WIP reorg functions.
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Signed-off-by: enriquezgarc <enriquezgarcia.external@infineon.com>
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@jaenrig-ifx
jaenrig-ifx committed Mar 25, 2024
1 parent 8c43451 commit a52aea7
Showing 1 changed file with 65 additions and 68 deletions.
133 changes: 65 additions & 68 deletions ports/psoc6/machine_i2s.c
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Original file line number Diff line number Diff line change
Expand Up @@ -8,15 +8,14 @@
mp_raise_msg_varg(&mp_type_ValueError, MP_ERROR_TEXT(msg), ret); \
}

// TODO: Are these values right?
/* Audio Subsystem Clock. Typical values depends on the desired sample rate:
* 8KHz / 16 KHz / 32 KHz / 48 KHz : 98.304 MHz
* 22.05 KHz / 44.1 KHz : 90.000 MHz
* 8KHz / 16 KHz / 32 KHz / 48 KHz : 98.304 MHz
* 22.05 KHz / 44.1 KHz : 90.3168 MHz
*/

/* Clock Settings */
#define AUDIO_SYS_CLOCK_HZ 98000000u /* in Hz (Ideally 98.304 MHz) */
#define AUDIO_SYS_CLOCK_HZ_1 90300000u
#define AUDIO_SYS_CLOCK_HZ_1 90300000u /* in Hz (Ideally 90.304 MHz) */

// uint32_t Audio_sys_clock_fz;
uint32_t Audio_sys_clock_fz = AUDIO_SYS_CLOCK_HZ;
Expand All @@ -27,7 +26,7 @@ cyhal_clock_t pll_clock;
cyhal_clock_t system_clock;
cyhal_clock_t hf0_clock;

// TODO: DMA ping-pong buffer size was empirically determined. It is a tradeoff between:
// DMA ping-pong buffer size was empirically determined. It is a tradeoff between:
// 1. memory use (smaller buffer size desirable to reduce memory footprint)
// 2. interrupt frequency (larger buffer size desirable to reduce interrupt frequency)
#define SIZEOF_DMA_BUFFER (256)
Expand Down Expand Up @@ -113,57 +112,64 @@ static int8_t get_frame_mapping_index(int8_t bits, format_t format) {
}
}

void clock_init(void) {
void i2s_audio_clock_init(void) {
cyhal_clock_t clock_pll;
cy_rslt_t result;

clock_set = 1;
static bool clock_set = 0;

/* Initialize, take ownership of PLL0/PLL */
result = cyhal_clock_reserve(&clock_pll, &CYHAL_CLOCK_PLL[0]);
if (CY_RSLT_SUCCESS != result) {
mp_printf(&mp_plat_print, "Clock reserve fail");
}
if (!clock_set) {

/* Set the PLL0/PLL frequency to AUDIO_SYS_CLOCK_HZ based on AUDIO_IN_SAMPLE_FREQ */
result = cyhal_clock_set_frequency(&clock_pll, Audio_sys_clock_fz, NULL);
if (CY_RSLT_SUCCESS != result) {
mp_printf(&mp_plat_print, "set_freq fail");
}
clock_set = 1;

/* If the PLL0/PLL clock is not already enabled, enable it */
if (!cyhal_clock_is_enabled(&clock_pll)) {
result = cyhal_clock_set_enabled(&clock_pll, true, true);
/* Initialize, take ownership of PLL0/PLL */
result = cyhal_clock_reserve(&clock_pll, &CYHAL_CLOCK_PLL[0]);
if (CY_RSLT_SUCCESS != result) {
mp_printf(&mp_plat_print, "PLL enable fail");
mp_printf(&mp_plat_print, "Clock reserve fail");
}
}

/* Initialize, take ownership of CLK_HF1 */
result = cyhal_clock_reserve(&audio_clock, &CYHAL_CLOCK_HF[1]);
if (CY_RSLT_SUCCESS != result) {
mp_printf(&mp_plat_print, "Clock Hf1 fail");
}
/* Set the PLL0/PLL frequency to AUDIO_SYS_CLOCK_HZ based on AUDIO_IN_SAMPLE_FREQ */
result = cyhal_clock_set_frequency(&clock_pll, Audio_sys_clock_fz, NULL);
if (CY_RSLT_SUCCESS != result) {
mp_printf(&mp_plat_print, "set_freq fail");
}

/* Source the audio subsystem clock (CLK_HF1) from PLL0/PLL */
result = cyhal_clock_set_source(&audio_clock, &clock_pll);
if (CY_RSLT_SUCCESS != result) {
mp_printf(&mp_plat_print, "sourcing HF1 fail");
}
/* If the PLL0/PLL clock is not already enabled, enable it */
if (!cyhal_clock_is_enabled(&clock_pll)) {
result = cyhal_clock_set_enabled(&clock_pll, true, true);
if (CY_RSLT_SUCCESS != result) {
mp_printf(&mp_plat_print, "PLL enable fail");
}
}

/* Set the divider for audio subsystem clock (CLK_HF1) */
result = cyhal_clock_set_divider(&audio_clock, 2);
if (CY_RSLT_SUCCESS != result) {
mp_printf(&mp_plat_print, "dividing hf1 fail");
}
/* Initialize, take ownership of CLK_HF1 */
result = cyhal_clock_reserve(&audio_clock, &CYHAL_CLOCK_HF[1]);
if (CY_RSLT_SUCCESS != result) {
mp_printf(&mp_plat_print, "Clock Hf1 fail");
}

/* Source the audio subsystem clock (CLK_HF1) from PLL0/PLL */
result = cyhal_clock_set_source(&audio_clock, &clock_pll);
if (CY_RSLT_SUCCESS != result) {
mp_printf(&mp_plat_print, "sourcing HF1 fail");
}

/* If the audio subsystem clock (CLK_HF1) is not already enabled, enable it */
if (!cyhal_clock_is_enabled(&audio_clock)) {
result = cyhal_clock_set_enabled(&audio_clock, true, true);
/* Set the divider for audio subsystem clock (CLK_HF1) */
result = cyhal_clock_set_divider(&audio_clock, 2);
if (CY_RSLT_SUCCESS != result) {
mp_printf(&mp_plat_print, "enable hf1 fail");
mp_printf(&mp_plat_print, "dividing hf1 fail");
}

/* If the audio subsystem clock (CLK_HF1) is not already enabled, enable it */
if (!cyhal_clock_is_enabled(&audio_clock)) {
result = cyhal_clock_set_enabled(&audio_clock, true, true);
if (CY_RSLT_SUCCESS != result) {
mp_printf(&mp_plat_print, "enable hf1 fail");
}
}
}

cyhal_system_delay_ms(1);
}

static inline bool i2s_dma_is_tx_complete(cyhal_i2s_event_t event) {
Expand Down Expand Up @@ -305,7 +311,7 @@ static void i2s_init(machine_i2s_obj_t *self, cyhal_clock_t *clock) {
i2s_assert_raise_val("I2S initialisation failed with return code %lx !", result);
}

static void i2s_dma_irq_configure(machine_i2s_obj_t *self) {
static inline void i2s_dma_irq_configure(machine_i2s_obj_t *self) {
cyhal_i2s_register_callback(&self->i2s_obj, &i2s_dma_irq_handler, self);

cyhal_i2s_event_t event;
Expand All @@ -316,13 +322,18 @@ static void i2s_dma_irq_configure(machine_i2s_obj_t *self) {
}

cyhal_i2s_enable_event(&self->i2s_obj, event, CYHAL_ISR_PRIORITY_DEFAULT, true);

cy_rslt_t result = cyhal_i2s_set_async_mode(&self->i2s_obj, CYHAL_ASYNC_DMA, CYHAL_DMA_PRIORITY_DEFAULT);
i2s_assert_raise_val("I2S set DMA mode failed with return code %lx !", result);
}

static void i2s_dma_rx_init(machine_i2s_obj_t *self) {
i2s_dma_rx(self);
static inline void i2s_dma_init_buff(machine_i2s_obj_t *self) {
for (uint32_t i = 0; i < SIZEOF_DMA_BUFFER; i++) {
self->dma_buffer[i] = 0;
}

cy_rslt_t result = cyhal_i2s_start_rx(&self->i2s_obj);
i2s_assert_raise_val("I2S rx start failed with return code %lx !", result);
self->dma_active_buf_p = self->dma_buffer;
self->dma_idle_buf_p = &self->dma_buffer[SIZEOF_HALF_DMA_BUFFER];
}

static void i2s_dma_tx_init(machine_i2s_obj_t *self) {
Expand All @@ -332,21 +343,15 @@ static void i2s_dma_tx_init(machine_i2s_obj_t *self) {
i2s_assert_raise_val("I2S tx start failed with return code %lx !", result);
}

static inline void i2s_dma_init_buff(machine_i2s_obj_t *self) {

for (uint32_t i = 0; i < SIZEOF_DMA_BUFFER; i++)
{
self->dma_buffer[i] = 0;
}
static void i2s_dma_rx_init(machine_i2s_obj_t *self) {
i2s_dma_rx(self);

self->dma_active_buf_p = self->dma_buffer;
self->dma_idle_buf_p = &self->dma_buffer[SIZEOF_HALF_DMA_BUFFER];
cy_rslt_t result = cyhal_i2s_start_rx(&self->i2s_obj);
i2s_assert_raise_val("I2S rx start failed with return code %lx !", result);
}

static void i2s_dma_init(machine_i2s_obj_t *self) {
cy_rslt_t result = cyhal_i2s_set_async_mode(&self->i2s_obj, CYHAL_ASYNC_DMA, CYHAL_DMA_PRIORITY_DEFAULT);
i2s_assert_raise_val("I2S set DMA mode failed with return code %lx !", result);

i2s_dma_irq_configure(self);
i2s_dma_init_buff(self);

void (*i2s_dma_mode_init_func)(machine_i2s_obj_t *self);
Expand All @@ -360,10 +365,10 @@ static void i2s_dma_init(machine_i2s_obj_t *self) {
i2s_dma_mode_init_func(self);
}



static void mp_machine_i2s_init_helper(machine_i2s_obj_t *self, mp_arg_val_t *args) {

// // TODO: with all inputs validated make the objects of the i2s object.
// // TODO: then make the i2s object
// TODO: validate all arguments before initializing or creating any object

// are Pins valid?
Expand Down Expand Up @@ -443,17 +448,9 @@ static void mp_machine_i2s_init_helper(machine_i2s_obj_t *self, mp_arg_val_t *ar
self->callback_for_non_blocking = MP_OBJ_NULL;
self->io_mode = BLOCKING;

// // i2s_clock_configure(); //Need to be in synch with user configurable clocks
if (clock_set == 0) {
clock_init();
cyhal_system_delay_ms(1);
}

// // TODO: with all inputs validated make the objects of the i2s object.
// // TODO: then make the i2s object
i2s_audio_clock_init();

i2s_init(self, &audio_clock);
i2s_dma_irq_configure(self);
i2s_dma_init(self);
}

Expand Down

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