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ports/psoc6/machine_i2s.c: Clock rework.
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Signed-off-by: enriquezgarc <enriquezgarcia.external@infineon.com>
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@jaenrig-ifx
jaenrig-ifx committed Mar 27, 2024
1 parent bd382f6 commit d464c53
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Showing 2 changed files with 41 additions and 34 deletions.
38 changes: 22 additions & 16 deletions ports/psoc6/machine_i2s.c
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Original file line number Diff line number Diff line change
Expand Up @@ -14,17 +14,15 @@
*/

/* Clock Settings */
#define AUDIO_SYS_CLOCK_HZ 98000000u /* in Hz (Ideally 98.304 MHz) */
#define AUDIO_SYS_CLOCK_HZ 98304000u /* in Hz (Ideally 98.304 MHz) */
#define AUDIO_SYS_CLOCK_HZ_1 90300000u /* in Hz (Ideally 90.304 MHz) */

// uint32_t Audio_sys_clock_fz;
uint32_t Audio_sys_clock_fz = AUDIO_SYS_CLOCK_HZ;
uint8_t clock_set;
// uint32_t Audio_sys_clock_fz = AUDIO_SYS_CLOCK_HZ;
// uint8_t clock_set;

cyhal_clock_t audio_clock;
cyhal_clock_t pll_clock;
cyhal_clock_t system_clock;
cyhal_clock_t hf0_clock;


// DMA ping-pong buffer size was empirically determined. It is a tradeoff between:
// 1. memory use (smaller buffer size desirable to reduce memory footprint)
Expand Down Expand Up @@ -112,15 +110,23 @@ static int8_t get_frame_mapping_index(int8_t bits, format_t format) {
}
}

void i2s_audio_clock_init(void) {
void i2s_audio_clock_init(uint32_t audio_clock_freq_hz) {
cyhal_clock_t clock_pll;
cy_rslt_t result;

static bool clock_set = 0;
static bool clock_set = false;
static uint32_t pll_source_clock_freq_hz = AUDIO_SYS_CLOCK_HZ;

if (audio_clock_freq_hz != pll_source_clock_freq_hz) {
clock_set = false;
pll_source_clock_freq_hz = audio_clock_freq_hz;
mp_printf(&mp_plat_print, "another clock configuration required\n");
}

if (!clock_set) {

clock_set = 1;
clock_set = true;
mp_printf(&mp_plat_print, "clock will be set\n");

/* Initialize, take ownership of PLL0/PLL */
result = cyhal_clock_reserve(&clock_pll, &CYHAL_CLOCK_PLL[0]);
Expand All @@ -129,7 +135,7 @@ void i2s_audio_clock_init(void) {
}

/* Set the PLL0/PLL frequency to AUDIO_SYS_CLOCK_HZ based on AUDIO_IN_SAMPLE_FREQ */
result = cyhal_clock_set_frequency(&clock_pll, Audio_sys_clock_fz, NULL);
result = cyhal_clock_set_frequency(&clock_pll, pll_source_clock_freq_hz, NULL);
if (CY_RSLT_SUCCESS != result) {
mp_printf(&mp_plat_print, "set_freq fail");
}
Expand Down Expand Up @@ -212,12 +218,12 @@ static void i2s_dma_from_dmabuf_to_ringbuf(machine_i2s_obj_t *self) {

uint8_t dma_sample_size_in_bytes = (self->bits == 16? 2 : 4) * (self->format == STEREO ? 2: 1);
uint8_t *dma_buff_p = (uint8_t *)self->dma_idle_buf_p;
uint32_t num_bytes_needed_from_ringbuf = SIZEOF_HALF_DMA_BUFFER * (I2S_RX_FRAME_SIZE_IN_BYTES / dma_sample_size_in_bytes);
uint32_t num_bytes_needed_from_ringbuf = SIZEOF_HALF_DMA_BUFFER_IN_BYTES * (I2S_RX_FRAME_SIZE_IN_BYTES / dma_sample_size_in_bytes);

// when space exists, copy samples into ring buffer
if (ringbuf_available_space(&self->ring_buffer) >= num_bytes_needed_from_ringbuf) {
uint8_t f_index = get_frame_mapping_index(self->bits, self->format);
for (uint32_t i = 0; i < SIZEOF_HALF_DMA_BUFFER; i += dma_sample_size_in_bytes) {
for (uint32_t i = 0; i < SIZEOF_HALF_DMA_BUFFER_IN_BYTES; i += dma_sample_size_in_bytes) {
for (uint8_t j = 0; I2S_RX_FRAME_SIZE_IN_BYTES; j++) {
int8_t r_to_a_mapping = i2s_frame_map[f_index][i];
if (r_to_a_mapping != -1) {
Expand Down Expand Up @@ -431,14 +437,15 @@ static void mp_machine_i2s_init_helper(machine_i2s_obj_t *self, mp_arg_val_t *ar
self->channel_resolution_bits = i2s_bits_resolution;
self->format = i2s_format;
self->rate = args[ARG_rate].u_int;
uint32_t audio_clock_freq_hz;
if (self->rate == 8000 ||
self->rate == 16000 ||
self->rate == 32000 ||
self->rate == 48000) {
Audio_sys_clock_fz = AUDIO_SYS_CLOCK_HZ;
audio_clock_freq_hz = AUDIO_SYS_CLOCK_HZ;
} else if (self->rate == 22050 ||
self->rate == 44100) {
Audio_sys_clock_fz = AUDIO_SYS_CLOCK_HZ_1;
audio_clock_freq_hz = AUDIO_SYS_CLOCK_HZ_1;
} else {
mp_raise_ValueError(MP_ERROR_TEXT("rate not supported"));
}
Expand All @@ -448,8 +455,7 @@ static void mp_machine_i2s_init_helper(machine_i2s_obj_t *self, mp_arg_val_t *ar
self->callback_for_non_blocking = MP_OBJ_NULL;
self->io_mode = BLOCKING;

i2s_audio_clock_init();

i2s_audio_clock_init(audio_clock_freq_hz);
i2s_init(self, &audio_clock);
i2s_dma_init(self);
}
Expand Down
37 changes: 19 additions & 18 deletions tests/psoc6/hw_ext/i2s.py
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Original file line number Diff line number Diff line change
Expand Up @@ -14,8 +14,8 @@
ws_rx_pin = "P5_5"
sd_rx_pin = "P5_6"
# while extmod/refactoring
print("SKIP")
raise SystemExit
# print("SKIP")
# raise SystemExit
elif "CY8CPROTO-063-BLE" in machine:
# This would be the right pins for this test, but unfortunately
# the P5_1 is allocated for the UART serial comm terminal communication.
Expand Down Expand Up @@ -56,6 +56,7 @@
rate=22050,
ibuf=20000,
)

# audio_in = I2S(
# 1,
# sck=sck_rx_pin,
Expand All @@ -68,32 +69,32 @@
# ibuf=20000,
# )

tx_done = False


def tx_complete_irq(obj):
global tx_done
tx_done = True
# print("tx completed")
# tx_done = False
# def tx_complete_irq(obj):
# global tx_done
# tx_done = True
# print("tx completed")

# def tx_complete_irq(obj):
# obj.write(buf)

# buf = b"\x01\x00\x17\x15\x16\x44"
# print("tx Buffer")
# print(buf)
audio_out.irq(tx_complete_irq)
# audio_out.irq(tx_complete_irq)
num_written = audio_out.write(buf)

while not tx_done:
pass
# while not tx_done:
# pass

print("tx completed")
print("tx blocking done")

# print(num_written)
# buf1 = bytearray(64)
# num_read = audio_in.readinto(buf1)
print(num_written)
# rx_buf = bytearray(sample_num)
# num_read = audio_in.readinto(rx_buf)
# print("Rx Buffer")
# print(buf1)
# print(rx_buf)
# audio_out.stop()
# audio_in.stop()
# time.sleep(5)
# time.sleep(20)
# audio_out.deinit()

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