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ports/psoc6: I2S test modify.
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Signed-off-by: IFX-Anusha <Anusha.TR@infineon.com>
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@IFX-Anusha
IFX-Anusha committed Oct 21, 2024
1 parent 3e43f3e commit e1be834
Showing 1 changed file with 96 additions and 96 deletions.
192 changes: 96 additions & 96 deletions ports/psoc6/modmachine.c
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Original file line number Diff line number Diff line change
Expand Up @@ -326,102 +326,102 @@ void cm4_set_frequency(uint32_t freq) {

}

void cm4_fll_set_frequency(uint32_t freq) {
cyhal_clock_t clock_fast;
cyhal_clock_t clock_slow;
cyhal_clock_t clock_fll;
cyhal_clock_t clock_hf0;
cyhal_clock_t clock_peri;

// deinitialize retarget-io before changing the clock frequency
cy_retarget_io_deinit();

/* Initialize, take ownership of PLL0/PLL */
cyhal_clock_reserve(&clock_fll, &CYHAL_CLOCK_FLL[0]);

/* Set the PLL0/PLL frequency to PLL_CLOCK_HZ =150 MHZ*/
cy_rslt_t result = cyhal_clock_set_frequency(&clock_fll, freq, NULL);
clock_assert_raise_val("FLL clock reserve failed with error code: %lx", result);

/* If the PLL0/PLL clock is not already enabled, enable it */
if (!cyhal_clock_is_enabled(&clock_fll)) {
result = cyhal_clock_set_enabled(&clock_fll, true, true);
clock_assert_raise_val("FLL clock enable failed with error code: %lx", result);
}

// HF0
/* Initialize, take ownership of CLK_HF0 */
result = cyhal_clock_reserve(&clock_hf0, &CYHAL_CLOCK_HF[0]);
clock_assert_raise_val("HF0 clock reserve failed with error code: %lx", result);

/* Source the (CLK_HF0) from PLL0/PLL */
result = cyhal_clock_set_source(&clock_hf0, &clock_fll);
clock_assert_raise_val("HF0 clock source failed with error code: %lx", result);

/* Set the divider for (CLK_HF0) */
result = cyhal_clock_set_divider(&clock_hf0, 1);
clock_assert_raise_val("HF0 clock set divider failed with error code: %lx", result);

/* (CLK_HF0) is not already enabled, enable it */
if (!cyhal_clock_is_enabled(&clock_hf0)) {
result = cyhal_clock_set_enabled(&clock_hf0, true, true);
clock_assert_raise_val("HF0 clock enable failed with error code: %lx", result);
}
// HF0

// Fast clock
result = cyhal_clock_reserve(&clock_fast, &CYHAL_CLOCK_FAST);
clock_assert_raise_val("Fast clock reserve failed with error code: %lx", result);

result = cyhal_clock_set_divider(&clock_fast, 1);
clock_assert_raise_val("Fast clock set divider failed with error code: %lx", result);



if (!cyhal_clock_is_enabled(&clock_fast)) {
result = cyhal_clock_set_enabled(&clock_fast, true, true);
clock_assert_raise_val("Fast clock enable failed with error code: %lx", result);
}
// Fast clock

// Peri clock
result = cyhal_clock_reserve(&clock_peri, &CYHAL_CLOCK_PERI);
clock_assert_raise_val("Peri clock reserve failed with error code: %lx", result);

result = cyhal_clock_set_divider(&clock_peri, 2);

if (!cyhal_clock_is_enabled(&clock_peri)) {
result = cyhal_clock_set_enabled(&clock_peri, true, true);
clock_assert_raise_val("Peri clock enable failed with error code: %lx", result);
}
// peri clock


// slow clock
result = cyhal_clock_reserve(&clock_slow, &CYHAL_CLOCK_SLOW);
clock_assert_raise_val("Slow clock reserve failed with error code: %lx", result);

result = cyhal_clock_set_divider(&clock_slow, 1);
clock_assert_raise_val("Slow clock set divider failed with error code: %lx", result);

if (!cyhal_clock_is_enabled(&clock_slow)) {
result = cyhal_clock_set_enabled(&clock_slow, true, true);
clock_assert_raise_val("Slow clock enable failed with error code: %lx", result);
}
// slow clock

cyhal_clock_free(&clock_fast);
cyhal_clock_free(&clock_slow);
cyhal_clock_free(&clock_pll);
cyhal_clock_free(&clock_hf0);
cyhal_clock_free(&clock_peri);

// Initialize retarget-io to use the debug UART port
result = cy_retarget_io_init(CYBSP_DEBUG_UART_TX, CYBSP_DEBUG_UART_RX, CY_RETARGET_IO_BAUDRATE);
if (result != CY_RSLT_SUCCESS) {
mp_raise_ValueError(MP_ERROR_TEXT("cy_retarget_io_init failed !\n"));
}
}
// void cm4_fll_set_frequency(uint32_t freq) {
// cyhal_clock_t clock_fast;
// cyhal_clock_t clock_slow;
// cyhal_clock_t clock_fll;
// cyhal_clock_t clock_hf0;
// cyhal_clock_t clock_peri;

// // deinitialize retarget-io before changing the clock frequency
// cy_retarget_io_deinit();

// /* Initialize, take ownership of PLL0/PLL */
// cyhal_clock_reserve(&clock_fll, &CYHAL_CLOCK_FLL[0]);

// /* Set the PLL0/PLL frequency to PLL_CLOCK_HZ =150 MHZ*/
// cy_rslt_t result = cyhal_clock_set_frequency(&clock_fll, freq, NULL);
// clock_assert_raise_val("FLL clock reserve failed with error code: %lx", result);

// /* If the PLL0/PLL clock is not already enabled, enable it */
// if (!cyhal_clock_is_enabled(&clock_fll)) {
// result = cyhal_clock_set_enabled(&clock_fll, true, true);
// clock_assert_raise_val("FLL clock enable failed with error code: %lx", result);
// }

// // HF0
// /* Initialize, take ownership of CLK_HF0 */
// result = cyhal_clock_reserve(&clock_hf0, &CYHAL_CLOCK_HF[0]);
// clock_assert_raise_val("HF0 clock reserve failed with error code: %lx", result);

// /* Source the (CLK_HF0) from PLL0/PLL */
// result = cyhal_clock_set_source(&clock_hf0, &clock_fll);
// clock_assert_raise_val("HF0 clock source failed with error code: %lx", result);

// /* Set the divider for (CLK_HF0) */
// result = cyhal_clock_set_divider(&clock_hf0, 1);
// clock_assert_raise_val("HF0 clock set divider failed with error code: %lx", result);

// /* (CLK_HF0) is not already enabled, enable it */
// if (!cyhal_clock_is_enabled(&clock_hf0)) {
// result = cyhal_clock_set_enabled(&clock_hf0, true, true);
// clock_assert_raise_val("HF0 clock enable failed with error code: %lx", result);
// }
// // HF0

// // Fast clock
// result = cyhal_clock_reserve(&clock_fast, &CYHAL_CLOCK_FAST);
// clock_assert_raise_val("Fast clock reserve failed with error code: %lx", result);

// result = cyhal_clock_set_divider(&clock_fast, 1);
// clock_assert_raise_val("Fast clock set divider failed with error code: %lx", result);



// if (!cyhal_clock_is_enabled(&clock_fast)) {
// result = cyhal_clock_set_enabled(&clock_fast, true, true);
// clock_assert_raise_val("Fast clock enable failed with error code: %lx", result);
// }
// // Fast clock

// // Peri clock
// result = cyhal_clock_reserve(&clock_peri, &CYHAL_CLOCK_PERI);
// clock_assert_raise_val("Peri clock reserve failed with error code: %lx", result);

// result = cyhal_clock_set_divider(&clock_peri, 2);

// if (!cyhal_clock_is_enabled(&clock_peri)) {
// result = cyhal_clock_set_enabled(&clock_peri, true, true);
// clock_assert_raise_val("Peri clock enable failed with error code: %lx", result);
// }
// // peri clock


// // slow clock
// result = cyhal_clock_reserve(&clock_slow, &CYHAL_CLOCK_SLOW);
// clock_assert_raise_val("Slow clock reserve failed with error code: %lx", result);

// result = cyhal_clock_set_divider(&clock_slow, 1);
// clock_assert_raise_val("Slow clock set divider failed with error code: %lx", result);

// if (!cyhal_clock_is_enabled(&clock_slow)) {
// result = cyhal_clock_set_enabled(&clock_slow, true, true);
// clock_assert_raise_val("Slow clock enable failed with error code: %lx", result);
// }
// // slow clock

// cyhal_clock_free(&clock_fast);
// cyhal_clock_free(&clock_slow);
// cyhal_clock_free(&clock_pll);
// cyhal_clock_free(&clock_hf0);
// cyhal_clock_free(&clock_peri);

// // Initialize retarget-io to use the debug UART port
// result = cy_retarget_io_init(CYBSP_DEBUG_UART_TX, CYBSP_DEBUG_UART_RX, CY_RETARGET_IO_BAUDRATE);
// if (result != CY_RSLT_SUCCESS) {
// mp_raise_ValueError(MP_ERROR_TEXT("cy_retarget_io_init failed !\n"));
// }
// }

void audio_i2s_set_frequency(uint32_t freq) {

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