Encryption node project on Zybo Z20 board
This repository contains source files for three types of projects: Vitis HLS, Vivado, and Vitis IDE all version 2021.2. A README located in each subdirectory contains instructions for building the respective project.
Vitis HLS is used for generating the RTL for the encrypt/decrypt kernels using a high-level C language description. A given kernel contains a source file with a top-level function, a header file containing type defintions and defines, a testbench source file for simulating the kernel functionality, and a test data header file to supply data to the testbench. After simulating the kernel, RTL can be generated by a synthesis command, and the RTL can be exported for use in a Vivado or Vitis design flow. This repository uses the Vivado design flow.
Vivado Design Suite can be used to structure a hieracrcy of RTL design files. Using the block diagram tool we can create a hardware platform including the processor system of the Zynq 7000, Xilinx IP, and custom IP such as the HLS kernel that we exported from Vitis HLS. To create a platform for our project, we can add a Zynq 7000 IP to our block diagram, and then import the HLS kernel IP and also add that to our block diagram. By cicking "Run block/connection automation" we can generated to remaining IP needed for project as well as the necessary connections between IP components. We can also use the block diagram tool to customize the IP we are using such as changing clock speeds, enabling Zynq peripherals, and changing base addresses of our AXI components.
Once we are happy with our block diagram, we can export our hardware platform to a .xsa file which can be imported by the Vitis IDE.
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